CS42518
LIST OF TABLES
Table 1. Common OMCK Clock Frequencies............................................................................................ 26
Table 2. Common PLL Output Clock Frequencies..................................................................................... 26
Table 3. Slave Mode Clock Ratios............................................................................................................. 27
Table 4. Serial Audio Port Channel Allocations ......................................................................................... 28
Table 5. DAC De-Emphasis....................................................................................................................... 49
Table 6. Receiver De-Emphasis ................................................................................................................ 49
Table 7. Digital Interface Formats.............................................................................................................. 50
Table 8. ADC One-Line Mode.................................................................................................................... 50
Table 9. DAC One-Line Mode.................................................................................................................... 50
Table 10. RMCK Divider Settings .............................................................................................................. 53
Table 11. OMCK Frequency Settings ........................................................................................................ 53
Table 12. Master Clock Source Select....................................................................................................... 54
Table 13. AES Format Detection ............................................................................................................... 55
Table 14. Receiver Clock Frequency Detection......................................................................................... 56
Table 15. Example Digital Volume Settings............................................................................................... 58
Table 16. ATAPI Decode ........................................................................................................................... 60
Table 17. Example ADC Input Gain Settings............................................................................................. 61
Table 18. TXP Output Selection................................................................................................................. 63
Table 19. Receiver Input Selection ............................................................................................................ 63
Table 20. Auxiliary Data Width Selection................................................................................................... 66
Table 21. External PLL Component Values & Locking Modes .................................................................. 77
6
DS584F1
CIRRUS [ CIRRUS LOGIC ]
