CS4281
CrystalClear™ PCI Audio Interface
EEPROM TIMING CHARACTERISTICS
Note 4. (T
A
= 0 to 70 °C, PCIVDD = CVDD = VAUX =
CRYVDD = 3.3 V; VDD5REF = 5 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V; Logic 0 = 0 V,
Logic 1 = 3.3 V; Timing reference levels = 1.4 V; PCI clock frequency = 33 MHz; unless otherwise noted)
Parameter
EECLK Low to EEDAT Data Out Valid
Start Condition Hold Time
EECLK Low
EECLK High
Start Condition Setup Time (for a Repeated Start Condition)
EEDAT In Hold Time
EEDAT In Setup Time
EEDAT/EECLK Rise Time
EEDAT/EECLK Fall Time
Stop Condition Setup Time
EEDAT Out Hold Time
(Note 18)
Symbol
t
AA
t
HD:STA
t
LEECLK
t
HEECLK
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
t
SU:STO
t
DH
Min
0
5.0
10
10
5.0
0
250
-
-
5.0
0
Max
7.0
-
-
-
-
-
-
1
300
-
-
Units
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
µs
Notes: 18. Rise time on EEDAT is determined by the capacitance on the EEDAT line with all connected gates and
the required external pull-up resistor.
t
F
EECLK
t
HEECLK
t
LEECLK
t
R
t
HD:DAT
EEDAT (IN)
t
SU:DAT
t
SU:STA
EEDAT (OUT)
t
HD:STA
t
AA
t
DH
t
SU:STO
EEDAT (OUT)
Figure 4. EEPROM Timing
CIRRUS LOGIC PRODUCT DATA SHEET
8
DS308PP4
CIRRUS [ CIRRUS LOGIC ]
