CS4329
SYSTEM DESIGN
Master Clock
The Master Clock, MCLK, is used to operate the
digital interpolation filter and the delta-sigma mod-
ulator. MCLK must be either 256×, 384× or 512×
the desired Input Sample Rate, Fs. Fs is the fre-
quency at which digital audio samples for each
channel are input to the DAC and is equal to the
LRCK frequency. The MCLK to LRCK frequency
ratio is detected automatically during the initializa-
tion sequence by counting the number of MCLK
transitions during a single LRCK period. Internal
dividers are then set to generate the proper clocks
for the digital filter, delta-sigma modulator and
switched-capacitor filter. LRCK must be synchro-
nous with MCLK. Once the MCLK to LRCK fre-
quency ratio has been detected, the phase and
frequency relationship between the two clocks
must remain fixed. If during any LRCK this rela-
tionship is changed, the CS4329 will reset. Table 1
illustrates the standard audio sample rates and the
required MCLK frequencies.
Fs
(kHz)
32
44.1
48
MCLK (MHz)
384x
12.2880
16.9344
18.4320
in 2's-complement format with the MSB-first in all
seven formats.
Formats 0, 1 and 2 are shown in Figure 3. The audio
data is right-justified, LSB aligned with the trailing
edge of LRCK, and latched into the serial input
data buffer on the rising edge of SCLK. Formats 0,
1 and 2 are 16, 18 and 20-bit versions and differ
only in the number of data bits required.
Formats 3 and 4 are 20-bit left justified, MSB
aligned with the leading edge of LRCK, and are
identical with the exception of the SCLK edge used
to latch data. Data is latched on the falling edge of
SCLK in Format 3 and the rising edge of SCLK in
Format 4. Both formats will support 16 and 18-bit
inputs if the data is followed by four or two zeros to
simulate a 20-bit input as shown in Figures 4 and 5.
A very small offset will result if the 18 or 16-bit
data is followed by static non-zero data.
Formats 5 and 6 are compatible with the I
2
S serial
data protocol and are shown in Figures 6 and 7. No-
tice that the MSB is delayed 1 period of SCLK fol-
lowing the leading edge of LRCK and LRCK is
inverted compared to the previous formats. Data is
latched on the rising edge of SCLK. Format 5 is 16-
bit I
2
S while Format 6 is 20-bit I
2
S. 18-bit I
2
S can
be implemented in Format 6 if the data is followed
by two zeros to simulate a 20-bit input as shown in
Figure 7. A very small offset will result if the 18-bit
data is followed by static non-zero data.
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
Format
0
1
2
3
4
5
6
Calibrate
Figure
3
3
3
4
5
6
7
-
256x
8.1920
11.2896
12.2880
512x
16.3840
22.5792
24.5760
Table 1. Common Clock Frequencies
Serial Data Interface
The Serial Data interface is accomplished via the
serial data input, SDATA, serial data clock, SCLK,
and the left/right clock, LRCK. The CS4329 sup-
ports seven serial data formats which are selected
via the digital input format pins DIF0, DIF1 and
DIF2. The different formats control the relation-
ship of LRCK to the serial data and the edge of
SCLK used to latch the data into the input buffer.
Table 2 lists the seven formats, along with the asso-
ciated figure number. The serial data is represented
Table 2. Digital Input Formats
8
DS153F1
CIRRUS [ CIRRUS LOGIC ]
