CS4330, CS4331, CS4333
LRCK
Left Channel
Right Channel
SCLK
SDATA
1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Internal SCLK Mode
Right Justified, 18-Bit Data
Data Valid on Rising Edge of SCLK
INT SCLK = 64 Fs if MCLK/LRCK = 256 or 512
INT SCLK = 48 Fs if MCLK/LRCK = 384
External SCLK Mode
Right Justified, 18-Bit Data
Data Valid on Rising Edge of SCLK
SCLK must have at least 36 cycles per LRCK
Figure 4. CS4330 Data Format
LRCK
SCLK
Left Channel
Right Channel
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Internal SCLK Mode
I
2
S, 16-Bit Data
Data Valid on Rising Edge of SCLK
INT SCLK = 32 Fs if MCLK/LRCK = 512 or 256
INT SCLK = 48 Fs if MCLK/LRCK = 384
Figure 5. CS4331 Internal SCLK Data Format (I
2
S)
10
DS136F1
CIRRUS [ CIRRUS LOGIC ]
