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CS4351-CZZ 参数 Datasheet PDF下载

CS4351-CZZ图片预览
型号: CS4351-CZZ
PDF下载: 下载PDF文件 查看货源
内容描述: 192 kHz立体声DAC 2 Vrms的线路输出 [192 kHz STEREO DAC WITH 2 Vrms LINE OUT]
分类和应用: 转换器数模转换器光电二极管
文件页数/大小: 41 页 / 1097 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS4351
4.9
Control Port Interface
The control port is used to load all the internal register settings (see section 6). The operation of the control
port may be completely asynchronous with the audio sample rate. However, to avoid potential interference
problems, the control port pins should remain static if no operation is required.
The control port operates in one of two modes: I
2
C or SPI.
4.9.1
MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit
(also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I
2
C writes
or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written,
allowing block reads or writes of successive registers.
4.9.2
I
2
C Mode
In the I
2
C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by
the serial control port clock, SCL (see Figure 9 for the clock to data relationship). There is no CS
pin. Pin AD0 enables the user to alter the chip address (100110[AD0][R/W]) and should be tied to
VL or GND as required, before powering up the device. If the device ever detects a high to low
transition on the AD0/CS pin after power-up, SPI mode will be selected.
4.9.2.1 I
2
C Write
To write to the device, follow the procedure below while adhering to the control port Switching
Specifications in section 7.
1) Initiate a START condition to the I
2
C bus followed by the address byte. The upper 6 bits
must be 100110. The seventh bit must match the setting of the AD0 pin, and the eighth must be
0. The eighth bit of the address byte is the R/W bit.
2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer,
MAP. This byte points to the register to be written.
3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register
pointed to by the MAP.
4) If the INCR bit (see section 4.9.1) is set to 1, repeat the previous step until all the desired
registers are written, then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I
2
C writes to other registers are desired, it is necessary
to initiate a repeated START condition and follow the procedure detailed from step 1. If no fur-
ther writes to other registers are desired, initiate a STOP condition to the bus.
4.9.2.2 I
2
C Read
To read from the device, follow the procedure below while adhering to the control port Switch-
ing Specifications.
DS566PP2
23