CS4362
9. DIAGRAMS
Left Channel
Right Channel
LRCK
SCLK
MSB
LSB
MSB
LSB
SDINx
+5 +4 +3 +2 +1
+5 +4 +3 +2 +1
-1 -2 -3 -4 -5
-1 -2 -3 -4
Figure 33. Format 0 - Left Justified up to 24-bit Data
Left Channel
Right Channel
LRCK
SCLK
SDINx
MSB
+5 +4 +3 +2 +1
LSB
MSB
+5 +4 +3 +2 +1
LSB
-1 -2 -3 -4 -5
-1 -2 -3 -4
Figure 34. Format 1 - I²S up to 24-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
9 8 7
6
5 4
3
2 1
0
9 8
15 14 13 12 11 10
7
6 5 4 3 2 1 0
15 14 13 12 11 10
32 clocks
Figure 35. Format 2 - Right Justified 16-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
7
6
5 4
3
2 1
0
7
6 5 4 3 2 1 0
0
23 22 21 20 19 18
32 clocks
23 22 21 20 19 18
Figure 36. Format 3 - Right Justified 24-bit Data
DS257F2
37
CIRRUS [ CIRRUS LOGIC ]
