CS4362
SWITCHING CHARACTERISTICS
(For KQZ T = -10°C to +70°C; VLS = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, C = 30 pF)
A
L
Parameters
Symbol
Min
Typ
Max
Units
MCLK Frequency
(Note 15)
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
1.024
6.400
6.400
40
-
-
51.2
51.2
51.2
60
MHz
MHz
MHz
%
-
MCLK Duty Cycle
Input Sample Rate
50
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs
4
50
100
-
-
-
50
100
200
kHz
kHz
kHz
LRCK Duty Cycle
45
20
20
50
-
55
-
%
ns
ns
SCLK Pulse Width Low
tsclkl
SCLK Pulse Width High
tsclkh
-
-
2
tsclkw
-
-
-
-
ns
ns
-----------------
SCLK Period
MCLK
4
tsclkw
-----------------
(Note 16)
(Note 17)
MCLK
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
LRCK1 to LRCK2 frequency ratio
tslrd
tslrs
tsdlrs
tsdh
20
-
-
ns
ns
ns
ns
20
-
-
20
-
-
-
-
20
0.25
1.00
4.00
Notes:
15. See Table 5 on page 27 for suggested MCLK frequencies
16. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.
17. The higher frequency LRCK must be an exact integer multiple (1, 2, or 4) of the lower frequency LRCK
.
LRCK
t
t
sclkh
slrs
t
slrd
t
sclkl
SCLK
t
t
sdh
sdlrs
SDATA
Figure 1. Serial Mode Input Timing
DS257F2
9
CIRRUS [ CIRRUS LOGIC ]
