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CS44600-CQZ 参数 Datasheet PDF下载

CS44600-CQZ图片预览
型号: CS44600-CQZ
PDF下载: 下载PDF文件 查看货源
内容描述: 6通道数字放大器控制器 [6-Channel Digital Amplifier Controller]
分类和应用: 放大器控制器
文件页数/大小: 76 页 / 1049 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS44600
7.15
Peak Limiter Control Register (address 15h)
6
RESERVED
5
RESERVED
4
RESERVED
3
RESERVED
2
RESERVED
1
LIMIT_ALL
0
LIMIT_EN
7
RESERVED
7.15.1 Peak Signal Limit All Channels (LIMIT_ALL)
Default = 0
0 - individual channel
1 - all channels
Function:
When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the
specific channel indicating clipping. The other channels will not be affected.
When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on
ALL
channels in response to
ANY
single channel indicating clipping.
7.15.2 Peak Signal Limiter Enable (LIMIT_EN)
Default = 0
0 - Disabled
1 - Enabled
Function:
The CS44600 will limit the maximum signal amplitude to prevent clipping when this function is enabled.
Peak Signal Limiting is performed by digital attenuation. The attack rate is determined by the Limiter At-
tack Rate register.
7.16
Limiter Attack Rate (address 16h)
6
ARATE6
5
ARATE5
4
ARATE4
3
ARATE3
2
ARATE2
1
ARATE1
0
ARATE0
7
ARATE7
7.16.1 Attack Rate (ARATE[7:0])
Default = 00010000
Function:
The limiter attack rate is user selectable. The effective rate is a function of the SRC output sampling fre-
quency and the value in the Limiter Attack Rate register. Rates are calculated using the function
RATE = (32/{value})/SRC Fs, where {value} is the decimal value in the Limiter Attack Rate register and
SRC Fs is the output sample rate of the SRC which is determined by the PWM master clock frequency.
SRC Fs equals 384 kHz for 24.576 MHz based clocks and 421.875 kHz for 27.000 MHz based clocks.
Note:
A value of zero in this register is not recommended, as it will induce erratic behavior of the limiter.
Use the LIM_EN bit to disable the limiter function (see
Peak Limiter Control Register (address 15h)).
DS633F1
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