CS44800
7.20.2 Overflow Level/Edge Select (OVFL_L/E)
Default = 0
Function:
This bit defines the OVFL interrupt type (0 = level sensitive, 1 = edge trigger). The Over Flow status of all
the audio channels when configured as “edge trigger” is cleared by reading the
Channel Over Flow Status
(address 2Bh) (Read Only),
and by reset. After a Reset this bit defaults to 0b, specifying “level sensitive”.
7.21
Interrupt Mask (address 29h)
2
1
0
M_OVFL_INT RESERVED RESERVED
7
6
5
4
3
M_SRC_UNLOCK M_SRC_LOCK M_RMPUP_DONE M_RMPDN_DONE M_MUTE_DONE
Default = 00000000
Function:
The bits of this register serve as a mask for the interrupt sources found in the Interrupt Status register. If a
mask bit is set to 1b, the interrupt is unmasked, meaning that its occurrence will affect the INT pin and the
Interrupt Status register. If a mask bit is set to 0b, the condition is masked, meaning that its occurrence will
not affect the INT pin. The bit positions align with the corresponding bits in the Interrupt Status register. The
mask bits for the GPIO_INT interrupt are located in the GPIO Interrupt Mask Register.
7.22
Interrupt Status (address 2Ah) (Read Only)
6
SRC_LOCK
5
RMPUP_DONE
4
RMPDN_DONE
3
MUTE_DONE
2
OVFL_INT
1
GPIO_INT
0
RESERVED
7
SRC_UNLOCK
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last
reading of the register. Reading the register resets the SRC_UNLOCK, SRC_LOCK, RMPUP_DONE,
RMPDN_DONE and MUTE_DONE bits to 0. These bits are considered “edge-trigger” interrupts.
The OVFL_INT and GPIO_INT bits will not reset to 0 by reading this register. The OVFL_INT bit will be set
to 0 by a read to the
“Channel Over Flow Status (address 2Bh) (Read Only)” on page 66
only when the in-
terrupt type is set to “edge-trigger”. The GPIO_INT bit will be set to 0 by a read to the
“GPIO Status Register
(address 2Fh)” on page 67
only when the interrupt type is set to “edge trigger”. If either of these interrupt
types are configured as “level sensitive”, then reading the appropriate status register will not clear the cor-
responding status bit in this register. OVFL_INT or GPIO_INT will remain set as long as the logic active level
is present. Once the level is cleared, then a read to the proper status register will clear the status bit.
7.22.1 SRC Unlock Interrupt (SRC_UNLOCK)
Default = 0
Function:
When high, indicates that the DAI interface has detected an error condition and/or the SRC has lost lock.
Conditions which cause the SRC to loose lock, such as loss of DAI_LRCK, DAI_MCLK or a DAI_LRCK/
DAI_MCLK ratio change, will cause an interrupt condition. This interrupt is an edge-triggered event.
If this bit is set to a 1b, indicating an unlock condition, and an SRC_LOCK interrupt is detected, then this
bit will be reset to 0b before a read of the Interrupt Status Register. Only the last valid state of the SRC
will be reported.
64
DS632F1
CIRRUS [ CIRRUS LOGIC ]
