CS4922
CLKIN by 300 and provides the divided clock to
33-bit-counter.
DSP
Clock
÷Q
÷2
CLKOUT
4.3 Digital to Analog Converter
The digital to analog converter (DAC) is a dual
channel CD quality DAC. It is designed with delta
sigma architecture. The baseband audio is interpo-
lated to 128Fs (192Fs) before going into the modu-
lator. The modulator is third order and is followed
by a 1 bit DAC/switch capacitor filter stage. An ex-
ternal passive filter completes the reconstruction
process. The output is single ended with a drive ca-
pability down to 8 kΩ. Figure 8 is a block diagram
of the DAC.
The interpolation filter produces images which are
attenuated by at least 56 dB from .584Fs to 128Fs
(192Fs). At a 48 kHz sample rate, a full scale signal
at 20 kHz will produce an image at 28 kHz which
is attenuated by more than 60 dB.
The out-of-band quantization noise from the delta
sigma modulator extends from .417Fs to 128Fs
(192Fs). This noise is attenuated by the switch ca-
pacitor filter and the continuous time filters. The
total quantization noise and thermal noise from the
analog filters integrated over the .417Fs to 128Fs
(192Fs) is more than 50 dB below full scale power.
Figure 7. CLKOUT Generation Circuit
The DSP clock is divided by a programmable di-
vider and an additional divide by 2 before being
output. The divider output is determined by the val-
ue of the Q value which can be accessed through
the application software. The divide by 2 guaran-
tees a 50% duty cycle output. The Q value provides
effective divides ranging from 1 to 1024, which
means the frequency of CLKOUT can vary from
the DSP clock frequency divided by 2 to the DSP
clock frequency divided by 2048. CLKOUT can be
used to synchronize external devices or generate
most compressed bit rate clocks.
4.2 33-bit Counter
The 33-bit-counter can be used to support MPEG
synchronization of audio and video. This loadable
counter is targeted to operate at 90 kHz. The
90 kHz clock may be derived from a 27 MHz mas-
ter clock provided at CLKIN (if available) or from
a 90 kHz clock provided at Pin 19 90_CLK. The se-
lection of the counter clock is made via the register
bit DIV which is accessible through the application
code. When set, the DIV bit divides the clock at
REG
16
D
A
C
SREG
D
A
C
L
Interpolation
Filter
Switched
Capacitor
Filter
Modulator
AOUTL
SREG
D
A
C
R
Interpolation
Filter
Switched
Capacitor
Filter
Modulator
AOUTR
I/O Data
Bus
Figure 8. DAC
16
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