CS4923/4/5/6/7/8/9
Although the memory can use more address bits,
typically only 16 bits of address space are used. For
this reason the memory example shown
incorporates a 2 latch memory architecture.
ABOOT can be released following the rising edge
of RESET. During the automatic boot cycle, the
serial control port should remain idle. Figure 23
shows an autoboot functional timing example.
The two latch external memory architecture is The autoboot cycle actually is a 24 bit, or three
required for the CS4926 or CS4928 when using address byte cycle. It should be noted that for
DTS. A three latch architecture can not be used
with the CS4926 or CS4928 running DTS since the
autoboot, the most significant byte is always zero.
For this reason a two latch external memory
run time memory access uses only 2 address cycles. configuration can be used for autoboot. The higher
order address byte simply shifts out of the memory
6.5.1 External Memory and Autoboot
latch and is discarded. If desired, a three latch
To configure the CS4923/4/5/6/7/8/9 to
automatically load its code from external memory,
the ABOOT signal should be driven low at the
rising edge of RESET. Once again this mode can
interface could also be used with the
CS4923/4/5/7/9 but it is not necessary.
For more information about autoboot and for a
thorough description of different external memory
architectures, reference the CS4923/4/5/6/7/8/9
Hardware User’s Guide.
2
only be chosen if either SPI or I C serial
communication is being used. In serial control port
mode, holding the ABOOT pin low as the CS492X
leaves the reset state enables an automatic boot.
RESET
ABOOT
EXTMEM
EMOE
EMWR
EMAD7:0
MA23:16
MA15:8
MA7:0
Data7:0
Figure 23. Autoboot Timing Diagram
DS262F2
43
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