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CS5102A-JL 参数 Datasheet PDF下载

CS5102A-JL图片预览
型号: CS5102A-JL
PDF下载: 下载PDF文件 查看货源
内容描述: 16位, 100 kSPS时/ 20 ksps的A / D转换器 [16-bit, 100 kSps / 20 kSps A/D Converters]
分类和应用: 转换器
文件页数/大小: 39 页 / 558 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5101A
CS5102A
16-bit, 100 kSps / 20 kSps A/D Converters
Features
Monolithic CMOS A/D Converters
– Inherent Sampling Architecture
– 2-channel Input Multiplexer
– Flexible Serial Output Port
Description
The CS5101A and CS5102A are 16-bit monolithic
CMOS analog-to-digital converters (ADCs) capable of
100 kSps (5101A) and 20 kSps (5102A) throughput. The
CS5102A’s low power consumption of 44mW, coupled
with a power-down mode, makes it particularly suitable
for battery-powered operation.
On-chip self-calibration circuitry achieves nonlinearity of
±0.001% of FS and guarantees 16-bit, no missing codes
over the entire specified temperature range. Superior lin-
earity also leads to 92 dB S/(N+D) with harmonics below
-100 dB. Offset and full-scale errors are minimized dur-
ing the calibration cycle, eliminating the need for external
trimming.
The CS5101A and CS5102A each consist of a 2-chan-
nel input multiplexer, DAC, conversion and calibration
microcontroller, clock generator, comparator, and serial
communications port. The inherent sampling architec-
ture of the device eliminates the need for an external
track-and-hold amplifier.
The converters’ 16-bit data is output in serial form with
either binary or two’s complement coding. Three output
timing modes are available for easy interfacing to micro-
controllers and shift registers. Unipolar and bipolar input
ranges are digitally selectable
ORDERING INFORMATION
See
Ultra-low Distortion
– S/(N+D): 92 dB
– TDH: 0.001%
Conversion Time
– CS5101A: 8µs
– CS5102A: 40
µs
Linearity Error:
±
0.001% FS
– Guaranteed No Missing Codes
Self-calibration Maintains Accuracy
– Accurate Over Time & Temperature
Low Power Consumption
– CS5101A: 320 mW
– CS5102A: 44 mW
I
HOLD SLEEPRST STBY CODE BP/UP CRS/FIN TRK1 TRK2 SSH/SDLSDATA
12
28
2
5
16
17
10
8
9
11
15
CLKIN
XOUT
REFBUF
VREF
AIN1
AIN2
CH1/2
AGND
3
4
21
20
19
24
13
22
Clock
Generator
14
Control
Calibration
SRAM
SCLK
-
+
-
+
-
+
25
VA+
23
VA-
Microcontroller
26
TEST
SCKMOD
OUTMOD
16-Bit Charge
Redistribution
DAC
-
+
Comparator
27
18
6
DGND
1
VD-
7
VD+
Copyright
©
Cirrus Logic, Inc. 2006
(All Rights Reserved)
JAN ‘06
DS45F6