CS5330A/31A
SCLK output
t mslr
LRCK output
t sdo
SDATA
SDATA
LRCK output
t sdo
SCLK output
t mslr
SCLK to SDATA LRCK - MASTER mode (CS5330A)
t slr1 t slr2
SCLK input
(SLAVE mode)
t sclkl t sclkh
SCLK to SDATA LRCK - MASTER mode (CS5331A)
t slr1 t slr2
SCLK input
(SLAVE mode)
t sclkl t sclkh
t
sclkw
LRCK input
(SLAVE mode)
t lrdss
SDATA
t dss
t
sclkw
LRCK input
(SLAVE mode)
t dss
SDATA
MSB
MSB-1
MSB-2
MSB
MSB-1
SCLK to LRCK & SDATA - SLAVE mode (CS5330A)
+5V
Analog
SCLK to LRCK & SDATA - SLAVE mode (CS5331A)
10
µF
+
0.1
µF
7
VA+
150
Ω
Analog
Input
Circuits
150
Ω
.47
µF
**
8
Audio Data
Processor
AINL
MCLK
SCLK
LRCK
SDATA
4
2
3
1
.01
µF
CS5330A
CS5331A
5
.01
µ
F
AINR
1 kΩ
1 kΩ
1 k
Ω
1 k
Ω
Timing
Logic
&
Clock
.47
µ
F
**
*
* Required for Master mode only
** Optional if analog input circuits biased
to within ± 5% of CS5330A/CS5331A
nominal input bias voltage
AGND
6
47 k
Ω
Figure 1. Typical Connection Diagram
8
DS138F5
CIRRUS [ CIRRUS LOGIC ]
