CS5364
4.11 Optimizing Performance in TDM Mode
Noise Management is a design technique that is utilized in the majority of audio A/D converters. Noise man-
agement is relatively simple conceptually. The goal of noise management is to interleave the on-chip digital
activity with the analog sampling processes to ensure that the noise generated by the digital activity is min-
imized (ideally non-existant) when the analog sampling occurs. Noise management, when implemented
properly, minimizes the on-chip interference between the analog and digital sections of the device. This
technique has proven to be very effective and has simplified the process of implementing an A/D converter
into a systems design. The dominate source of interference (and most difficult to control) is the activity on
the serial audio interface (SAI). However, noise management becomes more difficult to implement as audio
sample rates increase simply due to the fact that there is less time between transitions on the SAI.
The CS5364 A/D converter supports a multi-channel Time-Division-Multiplexed interface for Single, Double
and Quad-Speed sampling modes. In Single-Speed Mode, sample rates below 50 kHz, the required fre-
quencies of the audio serial ports are sufficiently low that it is possible to implement noise-management. In
this mode, the performance of the devices are relatively immune to activity on the audio ports.
However, in Double-Speed and Quad-Speed modes there is insufficient time to implement noise manage-
ment due to the required frequencies of the audio ports. Therefore, analog performance, both dynamic
range and THD+N, can be degraded if the serial port transitions occurr concurrently with the analog sam-
pling. The magnitude of the interference is not only related to the timing of the transition but also the di/dt or
transient currents associated with the activity on the serial ports. Even though there is insufficient time to
properly implement noise management, the interference effects can be minimized by controlling the tran-
sient currents required of the serial ports in Double- and Quad-Speed TDM Modes.
In addition to standard mixed-signal design techniques, system performance can be maximized by following
several guidelines during design.
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Operate the serial audio port at 3.3 V and not 5 V. The lower serial port voltage lowers transent
currents.
Operate the A/D converter as a system clock Slave. The serial clock and Left/Right clock become high-
impedence inputs in this mode and do not generate significant transient currents.
Place a buffer on the serial data output very near the A/D converter. Minimizing the stray capacitance
of the printed circuit board trace and the loading presented by other devices on the serial data line will
minimize the transient current.
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Place a resistor, near the converter, beween the A/D serial data output and the buffer. This resistor will
reduce the instantaneous switching currents into the capacitive loads on the nets, resulting in a slower
edge rate. The value of the resistor should be as high as possible without causing timing problems
elsewhere in the system.
4.12 DC Offset Control
The CS5364 includes a dedicated high-pass filter for each channel to remove input DC offset at the system
level. A DC level may result in audible “clicks” when switching between devices in a multi-channel system.
In Stand-Alone Mode, all of the high-pass filters remain enabled. In Control Port Mode, the high-pass filters
default to enabled, but may be controlled by writing to the HPF register. If any HPF bit is taken low, the re-
spective high-pass filter is enabled, and it continuously subtracts a measure of the DC offset from the output
of the decimation filter. If any HPF bit is taken high during device operation, the value of the DC offset reg-
ister is frozen, and this DC offset will continue to be subtracted from the conversion result.
DS625F2
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