CS5505/6/7/8
CS5505/6/7/8
5V SWITCHING CHARACTERISTICS
(T
A
= T
MIN
to T
MAX;
Parameter
Symbol
VA+, VD+ = 5V
±
10%;
VA- = -5V
±
10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C
L
= 50 pF.) (Note 2)
Min
Typ
Max
Units
SSC Mode (M/SLP = VD+)
Access Time:
SDATA Delay Time:
SCLK Delay Time
Serial Clock (Out)
Output Float Delay:
CS Low to SDATA out (DRDY = low)
DRDY falling to MSB (CS = low)
SCLK falling to next SDATA bit
SDATA MSB bit to SCLK rising
Pulse Width High
Pulse Width Low
CS high to output Hi-Z (Note 16)
SCLK rising to SDATA Hi-Z
t
csd1
t
dfd
t
dd1
t
cd1
t
ph1
t
pl1
t
fd1
t
fd2
f
sclk
Pulse Width High
Pulse Width Low
CS Low to data valid (Note 17)
(Note 18)
SCLK falling to new SDATA bit
CS high to output Hi-Z (Note 16)
SCLK falling to SDATA Hi-Z
t
ph2
t
pl2
t
csd2
t
dd2
t
fd3
t
fd4
-
-
-
-
-
-
-
-
-
2/f
clk
80
1/f
clk
1/f
clk
1/f
clk
-
1/f
clk
-
-
-
60
150
60
160
2/fclk
3/f
clk
250
-
-
-
2/f
clk
-
ns
ns
ns
ns
ns
ns
ns
ns
SEC Mode (M/SLP = DGND)
Serial Clock (In)
Serial Clock (In)
Access Time:
Maximum Delay time:
Output Float Delay:
0
200
200
-
-
-
-
2.5
-
-
200
310
150
300
MHz
ns
ns
ns
ns
ns
ns
Notes: 16. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete the
current data bit and then go to high impedance.
17. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high
for 2 clock cycles. The propagation delay time may be as great as 2 f clk cycles plus 200 ns. To
guarantee proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high
sooner than 2 fclk + 200 ns after CS goes low.
18. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
serial port shifting mechanism before falling edges can be recognized.
DS59F4
DS59F5
9
CIRRUS [ CIRRUS LOGIC ]
