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CS5513-BS 参数 Datasheet PDF下载

CS5513-BS图片预览
型号: CS5513-BS
PDF下载: 下载PDF文件 查看货源
内容描述: 16位和20位, 8引脚Σ-Δ型ADC [16-bit and 20-bit, 8-pin Sigma-Delta ADC]
分类和应用:
文件页数/大小: 24 页 / 408 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5510/11/12/13
2.5.3
Output Coding
20 bits are the conversion data, which is output
MSB first (Table 1).
Bits D22-D21 are the two flag bits. The OF (Over-
range Flag) bit is set to a logic 1 any time the input
signal is more positive than positive full scale, or
more negative than negative full scale. It is cleared
back to logic 0 whenever a conversion word occurs
which is not overranged. The OD (Oscillation De-
tect) bit is set to a logic 1 any time that an oscillatory
condition is detected in the modulator. This does
not occur under normal operating conditions, but
may occur whenever the input to the converter is ex-
As shown in Tables 1 and 2, the CS5510/11/12/13
present output conversions as 24-bit conversion
words. The first bit of the conversion word indi-
cates that a conversion is done through SDO fall-
ing from a logic high to a logic low level. The first
and the fourth bits output will always be zero. The
second and third bits are error flags, representing
an overflow or oscillation condition. In the
CS5510/11, there are four more bits of zero, and
the remaining 16 bits are the conversion data, out-
put MSB first (Table 2). In the CS5512/13, the final
CS
SCLK
SDO
0
OF
OD
0
0
0
0
0
M SB
LSB
0
0
D ata T im e
24 S C L K s
Figure 17. Data Word Timing for the CS5511.
CS
SC LK
SDO
0
OF OD
0
M SB
LSB
0
0
D a ta T im e
24 SC LKs
Figure 18. Data Word Timing for the CS5512.
CS
S C LK
SDO
0
OF
OD
0
M SB
LS B
0
0
D a ta T im e
24 S C LK s
Figure 19. Data Word Timing for the CS5513.
DS337F3
17