CS5521/22/23/24/28
SWITCHING CHARACTERISTICS
(T
A
= 25° C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%;
Levels: Logic 0 = 0 V, Logic 1 = VD+; C
L
= 50 pF.))
Parameter
Master Clock Frequency
(Note 25)
External Clock or Internal Oscillator (CS5522/24/28)
(CS5521/23)
Master Clock Duty Cycle
Rise Times
(Note 26)
Any Digital Input Except SCLK
SCLK
Any Digital Output
(Note 26)
Any Digital Input Except SCLK
SCLK
Any Digital Output
XTAL = 32.768 kHz
(Note 27)
t
rise
-
-
-
t
fall
-
-
-
t
ost
t
por
-
-
-
-
50
500
2006
1.0
100
-
-
-
µs
µs
ns
ms
XIN
cycles
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
50
1.0
100
-
µs
µs
ns
Symbol
XIN
30
30
40
32.768
32.768
-
200
130
60
kHz
kHz
%
Min
Typ
Max
Unit
Fall Times
Start-up
Oscillator Start-up Time
Power-on Reset Period
Serial Port Timing
Serial Clock Frequency
SCLK
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
0
100
250
250
50
50
100
100
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
-
-
-
-
-
-
-
150
150
150
SCLK Falling to CS Falling for continuous running SCLK
(Note 28)
Serial Clock
Pulse Width High
Pulse Width Low
SDI Write Timing
CS Enable to Valid Latch Clock
Data Set-up Time prior to SCLK rising
Data Hold Time After SCLK Rising
SCLK Falling Prior to CS Disable
SDO Read Timing
CS to Data Valid
SCLK Falling to New Data Bit
CS Rising to SDO Hi-Z
Notes: 25. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 200 kHz
(CS5522/24/28) or 130 kHz (CS5521/23) can be used for increased throughput.
26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
28. Applicable when SCLK is continuously running.
Specifications are subject to change without notice.
DS317F2
11
CIRRUS [ CIRRUS LOGIC ]
