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CS5521-AS 参数 Datasheet PDF下载

CS5521-AS图片预览
型号: CS5521-AS
PDF下载: 下载PDF文件 查看货源
内容描述: 16位或24位2/4/8通道ADC与PGIA [16 BIT OR 24 BIT 2/4/8 CHANNEL ADCS WITH PGIA]
分类和应用: 分布式控制系统DCS
文件页数/大小: 56 页 / 908 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5521/22/23/24/28
2.6 Digital Filter
The CS5521/22/23/24/28 have eight different lin-
ear phase digital filters which set the output word
rates (OWRs) shown in Table 3. These rates as-
sume that XIN is 32.768 kHz. Each of the filters
has a magnitude response similar to that shown in
Figure 18. The filters are optimized to settle to full
accuracy every conversion and yield better than
80 dB rejection for both 50 and 60 Hz with output
word rates at or below 15.0 Hz.
The converter’s digital filters scale with XIN. For
example with an output word rate of 15 Hz, the fil-
ter’s corner frequency is typically 12.7 Hz using a
32.768 kHz clock. If XIN is increased to
65.536 kHz the OWR doubles and the filter’s cor-
ner frequency moves to 25.4 Hz.
The converters will operate with an external
(CMOS compatible) clock with frequencies up to
130 kHz (CS5521/23) or 200 kHz (CS5522/24/28).
Figures 19 and 20 detail the CS5521/23 and
CS5522/24/28’s performance (respectively) at in-
creased clock rates.
The 32.768 kHz crystal is normally specified as a
time-keeping crystal with tight specifications for
both initial frequency and for drift over tempera-
ture. To maintain excellent frequency stability,
these crystals are specified only over limited oper-
ating temperature ranges (i.e. -10° C to +60° C).
However,
applications
with
the
CS5521/22/23/24/28 don’t generally require such
tight tolerances.
0.002
Linearity Error (%FS)
0.0018
0.0016
0.0014
0.0012
0.001
0.0008
0.0006
0.0004
30
50
70
90
110
130
XIN (kHz)
2.7 Clock Generator
The CS5521/22/23/24/28 include a gate which can
be connected with an external crystal to provide the
master clock for the chip. The chips are designed to
operate using a low-cost 32.768 kHz “tuning fork”
type crystal. One lead of the crystal should be con-
nected to XIN and the other to XOUT. Lead lengths
should be minimized to reduce stray capacitance.
Note that the oscillator circuit will also operate
with a 100 kHz “tuning fork” type crystal.
Figure 19. Typical Linearity Error for CS5521/23
0.0013
0.0012
Linearity Error (%FS)
0.0011
0.001
0.0009
0.0008
0.0007
0.0006
0.0005
0.0004
20
40
60
80
100 120 140 160 180 200
XIN (kHz)
Figure 18. Filter Response (Normalized to Output
Word Rate = 1)
Figure 20. Typical Linearity Error for CS5522/24/28
42
DS317F2