欢迎访问ic37.com |
会员登录 免费注册
发布采购

CS5530 参数 Datasheet PDF下载

CS5530图片预览
型号: CS5530
PDF下载: 下载PDF文件 查看货源
内容描述: 24位ADC,具有超低噪声放大器 [24-bit ADC with Ultra-low-noise Amplifier]
分类和应用: 放大器
文件页数/大小: 36 页 / 266 K
品牌: CIRRUS [ CIRRUS LOGIC ]
 浏览型号CS5530的Datasheet PDF文件第2页浏览型号CS5530的Datasheet PDF文件第3页浏览型号CS5530的Datasheet PDF文件第4页浏览型号CS5530的Datasheet PDF文件第5页浏览型号CS5530的Datasheet PDF文件第6页浏览型号CS5530的Datasheet PDF文件第7页浏览型号CS5530的Datasheet PDF文件第8页浏览型号CS5530的Datasheet PDF文件第9页  
CS5530
24-bit ADC
with
Ultra-low-noise Amplifier
Features
& Description
Chopper-stabilized
General Description
The CS5530 is a highly integrated
ΔΣ
Analog-to-Digital
Converter (ADC) which uses charge-balance techniques
to achieve 24-bit performance. The ADC is optimized for
measuring low-level unipolar or bipolar signals in weigh
scale, process control, scientific, and medical
applications.
To accommodate these applications, the ADC includes
a very-low-noise, chopper-stabilized instrumentation
amplifier (12 nV/√Hz @ 0.1 Hz) with a gain of 64X. This
device also includes a fourth-order
ΔΣ
modulator fol-
lowed by a digital filter which provides twenty selectable
output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,
120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and
3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADC and a micro-
controller, the converter includes a simple three-wire se-
rial interface which is SPI and Microwire compatible with
a Schmitt-trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options make this device an ideal
solution for weigh scale and process control
applications.
ORDERING INFORMATION
See page 35.
Instrumentation
Amplifier, 64X
• 12 nV/√Hz @ 0.1 Hz (No 1/f noise)
• 1200 pA Input Current
Digital
Gain Scaling up to 40x
Delta-sigma Analog-to-digital Converter
• Linearity Error: 0.0015% FS
• Noise Free Resolution: Up to 19 bits
Scalable
V
REF
Input: Up to Analog Supply
Simple Three-wire Serial Interface
• SPI™ and Microwire™ Compatible
• Schmitt-trigger on Serial Clock (SCLK)
Onboard
Offset and Gain Calibration
Registers
Word Rates: 6.25 to 3,840 Sps
50 or 60 Hz Rejection
Selectable
Selectable
Power
Supply Configurations
• VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
• VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
• VA+ = +3 V; VA- = -3 V; VD+ = +3 V
VA+
C1
C2
VREF+
VREF-
VD+
AIN1+
AIN1-
64X
DIFFERENTIAL
4
TH
ORDER
ΔΣ
MODULATOR
CS
PROGRAMMABLE
SINC FIR FILTER
SERIAL
INTERFACE
SDI
SDO
SCLK
LATCH
CLOCK
GENERATOR
CALIBRATION
SRAM/CONTROL
LOGIC
VA-
A0
A1
OSC1
OSC2
DGND
http://www.cirrus.com
Copyright
Cirrus Logic, Inc. 2009
(All Rights Reserved)
NOV ‘09
DS742F3