欢迎访问ic37.com |
会员登录 免费注册
发布采购

CS5532-BSZ 参数 Datasheet PDF下载

CS5532-BSZ图片预览
型号: CS5532-BSZ
PDF下载: 下载PDF文件 查看货源
内容描述: 24位ΔΣ ADC,以及超低噪音PGIA [24-bit ΔΣ ADCs with Ultra-low-noise PGIA]
分类和应用:
文件页数/大小: 50 页 / 733 K
品牌: CIRRUS [ CIRRUS LOGIC ]
 浏览型号CS5532-BSZ的Datasheet PDF文件第2页浏览型号CS5532-BSZ的Datasheet PDF文件第3页浏览型号CS5532-BSZ的Datasheet PDF文件第4页浏览型号CS5532-BSZ的Datasheet PDF文件第5页浏览型号CS5532-BSZ的Datasheet PDF文件第6页浏览型号CS5532-BSZ的Datasheet PDF文件第7页浏览型号CS5532-BSZ的Datasheet PDF文件第8页浏览型号CS5532-BSZ的Datasheet PDF文件第9页  
CS5532/34-BS
24-bit
∆Σ
ADCs
with
Ultra-low-noise PGIA
Features
Chopper-stabilized PGIA (Programmable
Gain Instrumentation Amplifier, 1x to 64x)
6 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x
1200 pA Input Current with Gains >1
General Description
The CS5532/34 are highly integrated
∆Σ
Analog-to-Digi-
tal Converters (ADCs) which use charge-balance
techniques to achieve 24-bit performance. The ADCs
are optimized for measuring low-level unipolar or bipolar
signals in weigh scale, process control, scientific, and
medical applications.
To accommodate these applications, the ADCs come as
either two-channel (CS5532) or four-channel (CS5534)
devices and include a very low-noise, chopper-stabilized
instrumentation amplifier (6 nV/√Hz @ 0.1 Hz) with se-
lectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and 64×.
These ADCs also include a fourth-order
∆Σ
modulator
followed by a digital filter which provides twenty selectable
output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,
120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and
3840 Sps (MCLK = 4.9152 MHz).
To ease communication between the ADCs and a micro-
controller, the converters include a simple three-wire se-
rial interface which is SPI™ and Microwire™ compatible
with a Schmitt-trigger input on the serial clock (SCLK).
High dynamic range, programmable output rates, and
flexible power supply options makes these ADCs ideal
solutions for weigh scale and process control
applications.
ORDERING INFORMATION
See
Delta-sigma Analog-to-digital Converter
Linearity Error: 0.0007% FS
Noise-free Resolution: Up to 23 bits
Two- or Four-channel Differential MUX
Scalable Input Span via Calibration
±5 mV to differential ±2.5V
Scalable V
REF
Input: Up to Analog Supply
Simple Three-wire Serial Interface
SPI™ and Microwire™ Compatible
Schmitt Trigger on Serial Clock (SCLK)
R/W Calibration Registers Per Channel
Selectable Word Rates: 6.25 to 3,840 Sps
Selectable 50 or 60 Hz Rejection
Power Supply Configurations
VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
VA+ = +3 V; VA- = -3 V; VD+ = +3 V
VA+
C1
C2
VREF+
VREF-
VD+
AIN1+
AIN1-
AIN2+
AIN2-
AIN3+
AIN3-
AIN4+
AIN4-
MUX
PGIA
1,2,4,8,16
32,64
DIFFERENTIAL
4
TH
ORDER
∆Σ
MODULATOR
CS
PROGRAMMABLE
SINC FIR FILTER
SERIAL
INTERFACE
SDI
SDO
SCLK
(CS5534
SHOWN)
CLOCK
GENERATOR
CALIBRATION
SRAM/CONTROL
LOGIC
LATCH
VA-
A0/GUARD
A1
OSC1
OSC2
DGND
Copyright
©
Cirrus Logic, Inc. 2008
(All Rights Reserved)
OCT ‘08
DS755F3