欢迎访问ic37.com |
会员登录 免费注册
发布采购

CS61583-IQ5 参数 Datasheet PDF下载

CS61583-IQ5图片预览
型号: CS61583-IQ5
PDF下载: 下载PDF文件 查看货源
内容描述: 双T1 / E1线路接口 [DUAL T1/E1 LINE INTERFACE]
分类和应用:
文件页数/大小: 44 页 / 708 K
品牌: CIRRUS [ CIRRUS LOGIC ]
 浏览型号CS61583-IQ5的Datasheet PDF文件第2页浏览型号CS61583-IQ5的Datasheet PDF文件第3页浏览型号CS61583-IQ5的Datasheet PDF文件第4页浏览型号CS61583-IQ5的Datasheet PDF文件第5页浏览型号CS61583-IQ5的Datasheet PDF文件第6页浏览型号CS61583-IQ5的Datasheet PDF文件第7页浏览型号CS61583-IQ5的Datasheet PDF文件第8页浏览型号CS61583-IQ5的Datasheet PDF文件第9页  
CS61583
Dual T1/E1 Line Interface
Features
General Description
The CS61583 is a dual line interface for T1/E1 applica-
tions, designed for high-volume cards where low power
and high density are required. Each channel features
individual control and status pins which eliminates the
need for external microprocessor support. The
matched impedance drivers reduce power consumption
and provide substantial return loss to insure superior
T1/E1 pulse quality.
hance system testability and reliability. The CS61583 is
a 5 volt device and is a hardware mode derivative of
the CS61584.
ORDERING INFORMATION
CS61583-IL5: 68-pin PLCC, -40 to +85 °C
CS61583-IQ5: 64-pin TQFP, -40 to +85 °C
Dual T1/E1 Line Interface
Low Power Consumption
(Typically 220mW per Line Interface)
Matched Impedance Transmit Drivers
Common Transmit and Receive Transform-
The CS61583 provides JTAG boundary scan to en-
ers for all Modes
Selectable Jitter Attenuation for Transmit
or Receive Paths
Supports JTAG Boundary Scan
Hardware Mode Derivative of the CS61584
RESET
CLKE
ATTEN2
CON11
TAOS1
RLOOP1
CON12
TAOS2
RLOOP2
AMI1
AMI2
ATTEN1
CODER1
CON01
CON21
LLOOP1
CODER2
CON02
CON22
LLOOP2
CONTROL
E
N
C
O
D
E
R
D
E
C
O
D
E
R
E
N
C
O
D
E
R
D
E
C
O
D
E
R
R
E
M
O
T
E
L
O
O
P
B
A
C
K
R
E
M
O
T
E
L
O
O
P
B
A
C
K
TCLK1
TPOS1/
TDATA1
TNEG1/
AIS1
RCLK1
RPOS1/
RDATA1
RNEG1/
BPV1
L
O
C
A
L
TAOS
PULSE
SHAPING
CIRCUITRY
TTIP1
DRIVER
TRING1
JITTER
ATTENUATOR
L
O
O
P
B
A
C
K
LOS
DETECT
CLOCK &
DATA
RECOVERY
RTIP1
RECEIVER
RRING1
TCLK2
TPOS2/
TDATA2
TNEG2/
AIS2
RCLK2
RPOS2/
RDATA2
RNEG2/
BPV2
L
O
C
A
L
TAOS
PULSE
SHAPING
CIRCUITRY
TTIP2
DRIVER
TRING2
JITTER
ATTENUATOR
L
O
O
P
B
A
C
K
LOS
DETECT
CLOCK &
DATA
RECOVERY
RTIP2
RECEIVER
RRING2
JTAG
4
CLOCK GENERATOR
2
REFCLK 1XCLK
LOS1 LOS2
2
2
2
3
2
TV+ TGND RV+ RGND DV+ DGND AV+ AGND BGREF
Crystal Semiconductor Corporation
P. O. Box 17847, Austin, Texas, 78760
(512) 445 7222 FAX:(512) 445 7581
Copyright
©
Crystal Semiconductor Corporation 1996
(All Rights Reserved)
JULY ’96
DS172PP5
1