CS8416
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Parameter
OSCLK/OLRCK Active Edge to SDOUT Output Valid
Master Mode
Symbol
Min
Typ
Max
Units
(Note 8)
tdpd
-
-
23
ns
RMCK to OSCLK active edge delay
RMCK to OLRCK delay
(Note 8)
(Note 9)
tsmd
tlmd
0
0
-
-
-
12
12
-
ns
ns
%
OSCLK and OLRCK Duty Cycle
Slave Mode
50
OSCLK Period
tsckw
tsckl
36
14
14
10
10
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
OSCLK Input Low Width
OSCLK Input High Width
tsckh
tlrckd
tlrcks
OSCLK Active Edge to OLRCK Edge
(Notes 8,9,10)
OSCLK Edge Setup Before OSCLK Active-Edge (Notes 8,9,11)
Notes:
8. In Software Mode the active edges of OSCLK are programmable.
9. In Software Mode the polarity of OLRCK is programmable.
10. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK
has changed.
11. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.
OSCLK
(output)
OLRCK
(input)
t
t
t
sckh
t
lrckd
lrcks
sckl
OLRCK
(output)
OSCLK
(input)
t
t
sckw
smd
t
lmd
t
dpd
RMCK
(output)
SDOUT
Figure 1. Audio Port Master Mode Timing
Figure 2. Audio Port Slave Mode and Data Input
DS578F3
9
CIRRUS [ CIRRUS LOGIC ]
