CS8422
24-bit, 192-kHz, Asynchronous Sample Rate Converter with
Integrated Digital Audio Interface Receiver
Sample Rate Converter Features
140 dB Dynamic Range
-120 dB THD+N
No External Master Clock Required
Supports Sample Rates up to 211 kHz
Input/Output Sample Rate Ratios from 6:1 to
Digital Audio Interface Receiver
Features
Complete EIAJ CP1201, IEC-60958, AES3,
1:6
Master Mode Master Clock/Sample Rate Ratio
VL
Support: 64, 96, 128, 192, 256, 384, 512, 768,
1024
16-, 18-, 20-, or 24-bit Data I/O
Dither Automatically Applied and Scaled to
Output Resolution
Multiple Device Outputs are Phase Matched
S/PDIF Compatible Receiver
28 kHz to 216 kHz Sample Rate Range
2:1 Differential AES3 or 4:1 S/PDIF Input Mux
De-emphasis Filtering for 32 kHz, 44.1 kHz,
and 48 kHz
Recovered Master Clock Output: 64 x Fs,
96 x Fs, 128 x Fs, 192 x Fs, 256 x Fs,
384 x Fs, 512 x Fs, 768 x Fs, 1024 x Fs
49.152 MHz Maximum Recovered Master
Clock Frequency
Ultra-low-jitter Clock Recovery
High Input Jitter Tolerance
No External PLL Filter Components Required
Selectable and Automatic Clock Switching
AES3 Direct Output and AES3 TX Pass-
through
On-chip Channel Status Data Buffering
Automatic Detection of Compressed Audio
Streams
Decodes CD Q Sub-Code
Level Translators
SDIN
ISCLK
ILRCK
Serial
Audio
Input
2:1
MUX
4:1
MUX
Receiver
Clock &
Data
Recovery
(PLL)
Sample
Rate
Converter
3:1
MUX
Serial
Audio
Output
SDOUT1
OSCLK1
OLRCK1
TDM_IN
RX0/RXP0
RX1/RXN0
RX2/RXP1
RX3/RXN1
VA
AGND
Clock
Generator
DGND
V_REG
Format
Detect
C or U Data Buffer
(First 5 Bytes)
3:1
MUX
Serial
Audio
Output
SDOUT2
OSCLK2
OLRCK2
Control Port & Registers
General
Purpose
Outputs
GPO0
GPO1
GPO2
GPO3
Level Translators
XTI XTO
RMCK
SDA/
SCL/
CDOUT CCLK
AD1/
CDIN
AD0/
CS
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright
Cirrus Logic, Inc. 2009
(All Rights Reserved)
MAY '09
DS692PP2
CIRRUS [ CIRRUS LOGIC ]
