CS8900A
Product Data Sheet
FEATURES
Single-Chip IEEE 802.3 Ethernet Controller with
Direct ISA-Bus Interface
Maximum Current Consumption = 55 mA (5V
Supply)
3 V or 5 V Operation
Industrial Temperature Range
Comprehensive Suite of Software Drivers
Available
Efficient PacketPage™ Architecture Operates in
I/O and Memory Space, and as DMA Slave
Full Duplex Operation
On-Chip RAM Buffers Transmit and Receive
Frames
10BASE-T Port with Analog Filters, Provides:
-
Automatic Polarity Detection and Correction
Crystal LAN™
Ethernet
Controller
DESCRIPTION
The CS8900A is a low-cost Ethernet LAN Controller op-
timized for the Industry Standard Architecture (ISA) bus
and general purpose microcontroller busses. Its highly-
integrated design eliminates the need for costly external
components required by other Ethernet controllers. The
CS8900A includes on-chip RAM, 10BASE-T transmit
and receive filters, and a direct ISA-Bus interface with
24 mA Drivers.
In addition to high integration, the CS8900A offers a
broad range of performance features and configuration-
options.
Its
unique
PacketPage
architecture
automatically adapts to changing network traffic pat-
terns and available system resources. The result is
increased system efficiency.
The CS8900A is available in a 100-pin LQFP package
ideally suited for small form-factor, cost-sensitive Ether-
net applications. With the CS8900A, system engineers
can design a complete Ethernet circuit that occupies
less than 1.5 square inches (10 sq. cm) of board space.
ORDERING INFORMATION
CS8900A-CQ
0° to 70° C
CS8900A-CQZ 0° to 70° C
CS8900A-IQ -40° to 85° C
CS8900A-IQZ -40° to 85° C
CS8900A-CQ3 0° to 70° C
CS8900A-CQ3Z 0° to 70° C
CS8900A-IQ3 -40° to 85° C
CS8900A-IQ3Z -40° to 85° C
CRD8900A-1
5V
LQFP-100
5V
LQFP-100
5V
LQFP-100
5V
LQFP-100
3.3V LQFP-100
3.3V LQFP-100
3.3V LQFP-100
3.3V LQFP-100
Evaluation Kit
AUI Port for 10BASE2, 10BASE5 and 10BASE-F
Programmable Transmit Features:
-
-
-
-
-
-
Automatic Re-transmission on Collision
Automatic Padding and CRC Generation
Stream Transfer™ for Reduced CPU Overhead
Auto-Switch Between DMA and On-Chip Memory
Early Interrupts for Frame Pre-Processing
Automatic Rejection of Erroneous Packets
Programmable Receive Features:
Lead free
Lead free
Lead free
Lead free
EEPROM Support for Jumperless Configuration
Boot PROM Support for Diskless Systems
Boundary Scan and Loopback Test
LED Drivers for Link Status and LAN Activity
Standby and Suspend Sleep Modes
EEPROM
20 MHz
XTAL
CS8900A ISA Ethernet Controller
EEPROM
Control
LED
Control
Clock
RAM
10BASE-T
RX Filters &
Receiver
10BASE-T
TX Filters &
Transmitter
RJ-45
10BASE-T
Host Bus
Bus
Logic
Host
Encoder/
Decoder
&
PLL
802.3
MAC
Engine
AUI
Transmitter
AUI
Collision
Memory
Manager
Boundary
Scan
Test Logic
Power
Manager
AUI
Receiver
Attachment
Unit
Interface
(AUI)
DS271F4
Copyright
©
Cirrus Logic, Inc. 2007
(All Rights Reserved)
AUG ‘07
CIRRUS [ CIRRUS LOGIC ]
