EP9315
Enhanced Universal Platform SOC Processor
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Timing and interface signals for digital LCD and TFT
displays
Full programmability for either non-interlaced or dual-
scan color and grayscale flat panel displays
Dedicated data path to SDRAM controller for
improved system performance
Pixel depths of 4, 8, 16, or 24 bits per pixel or 256
levels of grayscale
Hardware Cursor up to 64 x 64 pixels
256 x 18 Color Lookup Table
Hardware Blinking
8-bit interface to low end panel
Table F. LCD Interface Pin Assignments
only interrupts the processor when a meaningful change
occurs. The touch screen hardware may be disabled and
the switch matrix and ADC controlled directly if desired.
Features include:
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Support for 4-, 5-, 7-, or 8-wire analog resistive touch
screens.
Flexibility - unused lines may be used for temperature
sensing or other functions.
Touch screen interrupt function.
Table G. Touch Screen Interface with 12-bit Analog-to-Digital
Converter Pin Assignments
Pin Mnemonic
Xp, Xm
Yp, Ym
SXp, SXm
SYp, SYm
Pin Description
Touch screen ADC X Axis
Touch screen ADC Y Axis
Touch screen ADC X Axis
Voltage Feedback
Touch screen ADC Y Axis
Voltage Feedback
Pin Mnemonic
SPCLK
P[17:0]
HSYNC / LP
VCSYNC / FP
BLANK
BRIGHT
Pixel Clock
Pin Description
Pixel Data Bus [17:0]
Horizontal
Synchronization / Line Pulse
Vertical or Composite
Synchronization / Frame Pulse
Composite Blank
Pulse Width Modulated Brightness
64-Key Keypad Interface
The keypad circuitry scans an 8 x 8 array of 64 normally
open, single-pole switches. Any one or two keys
depressed will be de-bounced and decoded. An interrupt
is generated whenever a stable set of depressed keys is
detected. If the keypad is not utilized, the 16 column/row
pins may be used as general purpose I/O. The Keypad
interface:
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Provides scanning, debounce, and decoding for a 64-
key switch array.
Scans an 8-row by 8-column matrix.
May decode 2 keys at once.
Generates an interrupt when a new stable key is
determined.
Also generates a 3-key reset interrupt.
Table H. 64-Key Keypad Interface Pin Assignments
Graphics Accelerator
The EP9315 contains a hardware graphics acceleration
engine that improves graphic performance by handling
block copy, block fill and hardware line draw operations.
The Graphics Accelerator is used in the system to off-
load graphics operations from the processor.
Pixel depths supported by the Graphics Accelerator are
4, 8, 16 or 24 bits per pixel. The 24 bits per pixel mode
can be operated as packed (4 pixels every 3 words) or
unpacked (1 pixel per word with the high byte unused.)
The block copy operations of the Graphics Accelerator
are similar to a DMA (Direct Memory Access) transfer
that understands pixel organization, block width,
transparency, and transformation from 1bpp to higher 4,
8, 16 or 24bpp.
The line draw operations also allow for solid lines or
dashed lines. The colors for line drawing can be either
foreground color and background color or foreground
color with the background being transparent.
Pin Mnemonic
COL[7:0]
ROW[7:0]
Pin
Description
Key Matrix Column
Inputs
Key Matrix Row
Inputs
Alternative Usage
General Purpose I/O
General Purpose I/O
Touch Screen Interface with 12-bit Analog-
to-digital Converter (ADC)
The touch screen interface performs all sampling,
averaging, ADC range checking, and control for a wide
variety of analog resistive touch screens. This controller
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Copyright 2005 Cirrus Logic (All Rights Reserved)
DS638PP4
CIRRUS [ CIRRUS LOGIC ]
