PIC16F616/16HV616
TABLE 2-1:
Addr
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
INDF
TMR0
PCL
STATUS
FSR
PORTA
—
PORTC
—
—
PCLATH
INTCON
PIR1
—
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
PWM1CON
ECCPAS
—
VRCON
CM1CON0
CM2CON0
CM2CON1
—
ADRESH
ADCON0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
Program Counter’s (PC) Least Significant Byte
IRP
(1)
(1)
PIC16F616/16HV616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Page
Name
xxxx xxxx
xxxx xxxx
0000 0000
—
—
—
—
—
—
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
Indirect Data Memory Address Pointer
—
Unimplemented
—
Unimplemented
Unimplemented
—
GIE
—
Unimplemented
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1GINV
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
—
PEIE
ADIF
—
T0IE
CCP1IF
Write Buffer for upper 5 bits of Program Counter
INTE
C2IF
RAIE
C1IF
T0IF
—
INTF
TMR2IF
RAIF
TMR1IF
—
RC5
RC4
RC3
RC2
RC1
RC0
—
RA5
RA4
RA3
RA2
RA1
RA0
--x0 x000
—
--xx 00xx
—
—
---0 0000
0000 0000
-000 0-00
—
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
Timer2 Module Register
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
XXXX XXXX
XXXX XXXX
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
P1M1
PRSEN
ECCPASE
P1M0
PDC6
ECCPAS2
DC1B1
PDC5
ECCPAS1
DC1B0
PDC4
ECCPAS0
CCP1M3
PDC3
PSSAC1
CCP1M2
PDC2
PSSAC0
CCP1M1
PDC1
PSSBD1
CCP1M0
PDC0
PSSBD0
0000 0000
0000 0000
0000 0000
—
Unimplemented
C1VREN
C1ON
C2ON
MC1OUT
C2VREN
C1OUT
C2OUT
MC2OUT
VRR
C1OE
C2OE
—
VP6EN
C1POL
C2POL
T1ACS
VR3
—
—
C1HYS
VR2
C1R
C2R
C2HYS
VR1
C1CH1
C2CH1
T1GSS
VR0
C1CH0
C2CH0
C2SYNC
0000 0000
0000 -000
0000 -000
00-0 0010
—
xxxx xxxx
Unimplemented
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
ADFM
VCFG
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
0000 0000
Legend:
Note 1:
– = Unimplemented locations read as ‘0’,
u
= unchanged,
x
= unknown,
q
= value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
©
2006 Microchip Technology Inc.
Preliminary
DS41288A-page 9
CIRRUS [ CIRRUS LOGIC ]
