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T0514VL 参数 Datasheet PDF下载

T0514VL图片预览
型号: T0514VL
PDF下载: 下载PDF文件 查看货源
内容描述: [Low Capacitance ESD Protection Device]
分类和应用:
文件页数/大小: 9 页 / 906 K
品牌: CITC [ Chip Integration Technology Corporation ]
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T0514VL  
Low Capacitance ESD Protection Device  
Chip Integration Technology Corporation  
Features  
Applications  
Transient protection for high-speed data lines  
IEC 61000-4-2 (ESD) ±27kV (Air)  
±17kV (Contact)  
IEC 61000-4-4 (EFT) 40A (5/50 ns)  
Cable Discharge Event (CDE)  
Small package (2.9mm x 2.8mm x 1.4mm)  
Protects four data lines  
Low capacitance: 0.7pF Typical (I/O-GND)  
Low leakage current: 0.1uA@VRWM (Typical)  
Low clamping voltage  
Each I/O pin can withstand over 1000 ESD  
strikes for ±8kV contact discharge  
Green part  
Video Graphics Cards  
Desktops, Servers and Notebooks  
IEEE 1394 Ports  
USB 2.0/3.0 Power and Data Line Protection  
Display Ports  
SIM Ports  
Mechanical Characteristics  
SOT23-6L package  
Flammability Rating: UL 94V-0  
Marking: Part number  
Packaging: Tape and Reel  
Description  
Circuit Diagram  
VCC  
I/O_2  
I/O_4  
T0514VL is an ultra-low capacitance Transient  
Voltage Suppressor (TVS) designed to provide  
electrostatic discharge (ESD) protection for high-  
speed data interfaces. With typical capacitance of  
0.7pF only, T0514VL is designed to protect parasitic  
-sensitive system against over-voltage and over-current  
transient events. It complies with IEC61000-4-2(ESD)  
,Level 4 (±15kV air,±8kV contact discharge),IEC  
61000-4-4 (electrical fast transient - EFT) (40A,5/50ns)  
, very fast charged divice model (CDM)ESD and cable  
discharge event (СВE),etc.  
I/O_1  
GND  
I/O_3  
Pin Configuration  
I/O_2  
I/O_4  
VCC  
6
5
4
T0514VL user SOT23-6L package. Each  
T0514VL device can protect four high-speed data  
lines. The combined features of low capacitance, small  
size and high ESD robustness make  
ideal  
T0514VL  
for high-speed data ports and high-frequency lines  
(e.g., HDMI & DVI) applications. The low clamping  
voltage of theT0514VL guarantees a minimum stress  
on the protected IC.  
1
2
3
GND  
I/O_3  
I/O_1  
SOT23-6L  
(Top View)  
Document ID : DS-22V18  
Revised Date : 2017/07/20  
Revision : C  
1