M-8870
In a single-ended configuration, the input pins are
connected as shown in the Single - Ended Input
Configuration on page 3 with the op-amp connected
stops the oscillator and the functioning of the filters.
On the M-8870-01 models, this pin is tied to ground
(logic low).
for unity gain and VREF biasing the input at 1/2VDD
The Differential Input Configuration bellow permits
gain adjustment with the feedback resistor R5.
.
Inhibit mode is enabled by a logic high input to pin 5
(INH). It inhibits the detection of 1633 Hz. The output
code will remain the same as the previous detected
code (see Pin functions table on page 4). On the M-
8870-01 models, this pin is tied to ground (logic low).
DTMF Clock Circuit
The internal clock circuit is completed with the addition
of a standard 3.579545 MHz television color burst crys-
tal. The crystal can be connected to a single M-8870 as
shown in the Single - Ended Input Configuration on
page 3, or to a series of M-8870s. As illustrated in the
Common Crystal Connection below, a single crystal
can be used to connect a series of M-8870s by cou-
pling the oscillator output of each M-8870 through a 30
pF capacitor to the oscillator input of the next M-8870.
Input Configuration
The input arrangement of the M-8870 provides a dif-
ferential input operational amplifier as well as a bias
source (VREF) to bias the inputs at mid-rail. Provision
is made for connection of a feedback resistor to the
op-amp output (GS) for gain adjustment.
Tone Decoding
FLOW
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
ANY
FHIGH
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
ANY
Key (ref.)
OE
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
Q4
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Z
Q3
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Z
Q2
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Z
Q1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Z
1
2
3
4
5
6
7
8
9
0
S
#
A
B
C
D
ANY
L = logic low, H = logic high, Z = high impedance
Common Crystal Connection
Differential Input Configuration
Rev. 3
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