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CMX589AP4 参数 Datasheet PDF下载

CMX589AP4图片预览
型号: CMX589AP4
PDF下载: 下载PDF文件 查看货源
内容描述: 调制解调器电路| MODEM | CMOS | DIP | 24PIN |塑料\n [MODEM CIRCUIT|MODEM|CMOS|DIP|24PIN|PLASTIC ]
分类和应用: 调制解调器
文件页数/大小: 23 页 / 556 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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GMSK Modem
CMX589A
2 Signal List
Pin No.
E2/D5/
D2/P4
1
2
Signal
Type
Description
XTALN
XTAL/CLOCK
O/P
I/P
The output of the on-chip clock oscillator.
The input to the on-chip Xtal oscillator. A Xtal, or externally derived
clock (f
XTAL
) pulse input should be connected here. If an externally
generated clock is to be used, it should be connected to this pin and the
XTALN pin left unconnected. Note: Operation without a suitable Xtal or
clock input may cause device damage.
Logic level inputs control the internal clock divider and therefore the
transmit and receive data rate. See Table 4.
Logic level inputs control the internal clock divider and therefore the
transmit and receive data rate. See Table 4.
A logic ‘0’ applied to this input will freeze the Clock Extraction and Level
Measurement circuits unless they are in ‘Acquire’ mode.
A logic ‘1’ applied to this input will set the Rx Level Measurement
circuitry to the ‘Acquire’ mode. See Table 6.
A logic ‘1’ applied to this input will set the Rx Clock Extraction circuitry
to the ‘Acquire’ mode. See Table 5.
A logic ‘1’ applied to this input will powersave all receive circuits except
for Rx CLK output (which will continue at the set bit-rate) and cause the
Rx Data and Rx S/N outputs to go to a logic ‘0’.
The internal circuitry bias line, held at V
DD
/2. This pin must be
bypassed to V
SS
by a capacitor mounted close to the pin.
Output of the Rx Input Amplifier.
Input to Rx input amplifier.
Negative supply (GND).
Connections to the Rx Level Measurement Circuitry. A capacitor should
be connected from this pin to V
SS
.
Connections to the Rx Level Measurement Circuitry. A capacitor should
be connected from this pin to V
SS
.
A logic level to select the modem BT (the ratio of the Tx Filter's -3dB
frequency to the Bit-Rate). A logic ‘1’ = BT of 0.5 and a logic ‘0’ = BT of
0.3.
3
4
5
6
7
8
ClkDivA
ClkDivB
RxHOLDN
RxDCacq
PLLacq
Rx PSAVE
I/P
I/P
I/P
I/P
I/P
I/P
9
10
11
12
13
14
15
V
BIAS
Rx FB
Rx Signal In
V
SS
DOC1
DOC2
BT
power
O/P
I/P
power
O/P
O/P
I/P
©
2002 CML Microsystems Plc
4
D/589A/4