The gain of each amplifier block (Channel 1 to Channel 8)
in the FX009A is set by a separate 8-bit data word ( bit 7
to bit 0 ). This 8-bit word, consisting of 4 Address bits (bit
7 to bit 4) and 4 Gain Control bits (bit 3 to bit 0), is loaded
to the Control Data Input in serial format using the external
data clock.
Data is loaded to the FX009A on the rising edge of the
Serial Clock. Loaded data is executed on the falling
(rising) edge of the Load/Latch (Load/Latch) pulse. Table
1 shows the format of each 4-bit Address word, Table 2
shows the format of each Gain Control word with Figure 4
describing the data loading operation and timing.
Table 1 Address Word Format
Bit 7
MSB
1
1
1
1
1
1
1
1
Bit 6
0
0
0
0
1
1
1
1
Bit 5
0
0
1
1
0
0
1
1
Bit 4
LSB
0
1
0
1
0
1
0
1
Channel
Selected
1
2
3
4
5
6
7
8
Table 2 Gain Control Word Format
Bit 3
MSB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Bit 0
LSB
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Stage 1 to 7
(0.43dB)
Powersave
-3.0
-2.571
-2.143
-1.714
-1.286
-0.857
-0.428
0
0.428
0.857
1.286
1.714
2.143
2.571
3.0
Stage 8
(2.0dB)
Powersave
-14.0 dB
-12.0 dB
-10.0 dB
-8.0 dB
-6.0 dB
-4.0 dB
-2.0 dB
0
dB
2.0
dB
4.0
dB
6.0
dB
8.0
dB
10.0 dB
12.0 dB
14.0 dB
Data Loading
The 8-bit data word is loaded
bit 7 first and bit 0
last.
Bit 7 must be a logic “1” to address the chip.
If bit 7 in the word is a logic “0” that 8-bit word will not be
executed. Figure 4 (below) shows the timing information
required to load and operate this device.
SERIAL DATA CLOCK
t
PWH
t
PWL
SERIAL DATA IN
(ONE 8-BIT WORD)
t
DS
t
DH
Loaded Last
BIT 6
BIT 1
BIT 0
8th
Clock
Pulse
Next
Clock
Pulse
Logic ’1’
Loaded
First
BIT 7
LOAD/LATCH
t
LLD
t
LLW
t
LLO
LOAD/LATCH
Timing
t
PWH
Serial Clock "High" Pulse Width
t
PWL
Serial Clock "Low" Pulse Width
t
DS
Data Set-up Time
t
DH
Data Hold Time
t
LLD
Load/Latch Delay
t
LLW
Load/Latch Pulse Width
t
LLO
Load/Latch Over Time
Fig.4 Serial Control Data Loading Diagram
4
CMLMICRO [ CML MICROCIRCUITS ]
