FX802
DVSR C
ODEC
SERIAL
CLOCK
COMMAND
DATA
REPLY
DATA
CS
IRQ
XTAL/
CLOCK
XTAL
AUDIO
IN
AUDIO
BYPASS
AUDIO
OUT
C-BUS INTERFACE AND CONTROL LOGIC
CLOCK
GENERATOR
DECODER
OUTPUT
V
BIAS
CONTROL
PLAY
COMMAND
BUFFER
STORE
COMMAND
BUFFER
REGISTER
STATUS
REGISTER
ENCODE
CLOCK
DECODE
CLOCK
DATA
READ
COUNTER
DATA
WRITE
COUNTER
SPEECH
PLAY
COUNTERS
SPEECH
STORE
COUNTERS
ENCODER
CLOCK
DECODER
CLOCK
POWER
ASSESS
MOD
DEMOD
IDLE
PATTERN
DRAM CONTROL AND TIMING
DIRECT ACCESS CLOCKS and DATA
WE
CAS
RAS 1 RAS 2 RAS 3 RAS 4
A9
A8
A7
A6
A5
A4
A3/ECK
A2/DCK
A0/ENO
(ENCODER
OUT)
A1/ DEI
(DECODER
IN)
V
DD
DRAM ADDRESS LINES
V
BIAS
V
SS
Fig.1 FX802 DVSR Codec
Brief Description
The FX802 DVSR Codec contains:
A Continuously Variable Slope Delta Modulation (CVSD)
encoder and decoder.
Control and timing circuitry for up to 4Mbits of external
Dynamic Random Access Memory (DRAM).
“C-BUS”
µProcessor
interface and control logic.
When used with external DRAM, the FX802 has four primary
functions:
q
Speech Storage
Speech signals present at the Audio Input may be digitized
by the CVSD encoder, and the resulting bit stream stored
in DRAM. This process also provides readings of input
power level for use by the system
µController.
q
Speech Playback
Previously digitized speech data may be read from DRAM
and converted back into analogue form by the CVSD
decoder.
q
Data Storage
Digital data sent over the “C-BUS” from the system
µController
may be stored in DRAM.
q
Data Retrieval
Digital data may be read from DRAM and sent over
“C-BUS” to the system
µController.
Speech storage and playback may be performed
concurrently with data storage or retrieval.
The FX802 may also be used without DRAM (as a “stand-
alone” CVSD Codec), in which case direct access is
provided to the CVSD Codec digital data and clock signals.
All functions are controlled by “C-BUS” commands from
the system
µController.
The Storage, Recovery and Replay functions of the
FX802 can be used for:
q
Answering Machine applications, where an incoming
speech message is stored for later recall.
q
Busy Buffering, an outgoing speech message is stored
temporarily until the transmit channel becomes free.
q
Automatic transmission of pre-recorded ‘Alarm’ or
status announcements.
q
Time Domain Scrambling of speech messages.
q
VOX control of transmitter functions.
q
Temporary Data Storage applications, such as
buffering of over-air data transmissions.
On-chip the Delta Codec is supported by input and output
analogue switched-capacitor filters and audio output
switching circuitry. The DRAM control and timing circuitry
provides all the necessary address, control and refresh
signals to interface to external DRAM.
The FX802 DVSR Codec is a low-power 5-volt CMOS LSI
device.
Publication D/802/4 December 1995
CMLMICRO [ CML MICROCIRCUITS ]
