FX805 Sub-Audio
Signalling Processor
Rx SUB-AUDIO
OUT
Rx LOWPASS
Rx SUB-AUDIO
IN
COMPARATOR
IN
OUT
+
–
180Hz/260Hz
COMPARATOR
AMP
Raw NRZ “Data”
DIGITAL
NOISE
FILTER
FREQUENCY
ASSESMENT
NOTONE
TIMER
NOTONE
OUT
NRZ Rx
DATA and
BAUD RATE
EXTRACTOR
NRZ
Rx Data
Rx
V
BIAS
Tx
DATA BUFFER
XTAL/CLOCK
CLOCK
GENERATOR
XTAL
NRZ Tx BAUD
RATE
CTCSS
Tx TONE
NRZ Rx
CLOCK RATE
Audio Signal Path
AUDIO IN
Audio By-Pass
CTCSS “Sub-Audio” Frequency
SUB-AUDIO BANDSTOP
Tx LEVEL
ADJUST
and
SHIFT REGISTER
NRZ Tx Data
Variable
Bandwidth
NRZ
Rx Baud Rate
FREQUENCY
MEASUREMENT
(COUNTER)
C-BUS
INTERFACE
AND
CONTROL
LOGIC
COMMAND DATA
REPLY DATA
CHIP SELECT
INTERRUPT
SERIAL CLOCK
WAKE
ADDRESS SELECT
+
IN
–
Rx AMP
V
DD
Tx
SUB-AUDIO
OUT
V
SS
Tx SUB-AUDIO LOWPASS
AUDIO OUT
Fig.1 FX805 Sub-Audio Signalling Processor
FX805 Sub-Audio Signalling Processor
A
µProcessor
controlled, sub-audio frequency signalling
processor to provide an outband audio and digital signalling
facility for PMR radio systems.
This device caters for the transmission and non-predictive
reception of:
q
Continuous Tone Controlled Squelch (CTCSS) tones
and other non-standard sub-audio frequencies.
q
Non-Return-to-Zero (NRZ) data to facilitate Continuous
Digitally Coded Squelch (CDCS/DPL
™
) system
operations.
To achieve these functions, the FX805 has on-chip:
q
A non-predictive CTCSS Tone Decoder and CDCS sub-
audio signal demodulator.
q
A CTCSS/NRZ Encoder with Tx level adjustment and
lowpass filter output stage with optional NRZ
pre-emphasis.
q
A selectable sub-audio bandstop filter.
q
A Notone (CTCSS Rx) period timer.
Setting of the FX805 functions and modes is by data
loaded from the
µController
to the controlling registers within
the device. Reply Data and Interrupt protocol keep the
µController
up to date on the operational status of the
circuitry –– all via the “C-BUS” interface.
CTCSS
tone data for transmission is generated within the
µController,
loaded to CTCSS Tx Frequency Register,
encoded and output as a tone via the Tx Sub-Audio Lowpass
Filter.
™
Received non-predicted CTCSS tone frequencies are
measured and the resulting data, in the form of a 2-byte
data-word, is presented via the CTCSS Rx Frequency
Register to the
µController
for matching against a ‘look-up’
table. Noise filtering is provided to improve the signal quality
prior to measurement.
NRZ
coded data streams for transmission, when
generated within a
µController,
are loaded to the NRZ Tx
Data Buffer and output, in 8-bit bytes, through the Lowpass
Filter circuitry as sub-audio signals. CDCS turn-off tones can
be added to the data signals by switching the FX805 to the
CTCSS transmit mode at the appropriate time.
NRZ coding is produced by the
µController
and translated
into sub-audio signals by the FX805.
Received NRZ data is filtered, detected and placed into
the NRZ Rx Data Register which is then available for transfer
one byte at a time, to the
µController,
for decoding by
software. Clock extraction circuitry is provided on chip and
Rx and Tx baud rates are selectable.
Provision is made in both hardware and system software
allocations to address two FX805 Sub-Audio Signalling
Processors consecutively to achieve multi-mode, duplex
operation.
The FX805 has a powersaving function which may be
controlled by software or a dedicated (Wake) input.
The FX805 is a low-power, 5-volt CMOS integrated circuit
and is available in 24-pin DIL cerdip and 24-pin/lead plastic
SMD packages.
DPL is a registered trademark of Motorola Inc.
Publication D/805/3 July 1994
CMLMICRO [ CML MICROCIRCUITS ]
