CTCSS/DCS/SELCALL Processor
FX828
Write Only Register Description
GENERAL RESET (Hex address $01)
The reset command has no data attached to it.
powersaved) states as listed below:
REGISTER NAME
SIGNALLING CONTROL
SELCALL & SUB-AUDIO STATUS
SIGNALLING SET-UP
CTCSS TX / FAST RX FREQUENCY
CTCSS TX / FAST RX FREQUENCY
RX TONE PROGRAM
RX TONE PROGRAM
DCS BYTE 3
DCS BYTE 2
DCS BYTE 1
GENERAL CONTROL
AUDIO CONTROL
AUDIO CONTROL
GENERAL PURPOSE TIMER
SELCALL TX
SELCALL TX
IRQ MASK
IRQ FLAG
HEX
ADDRESS
$80
$81
$82
$83
$84
$85
$86
$87
$88
$8A
$8B
$8D
$8E
$8F
It sets the device registers into the specific (all
(1)
(2)
(1)
(2)
(1)
(2)
(1)
(2)
BIT 7
(D7)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 6
(D6)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 5
(D5)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 4
(D4)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 3
(D3)
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 2
(D2)
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 1
(D1)
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT 0
D0)
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X = undefined
SIGNALLING CONTROL Register (Hex address $80)
This register is used to control the functions of the device as described below:
SUBAUDIO TX
ENABLE
(Bit 7)
TONE DECODER
ENABLE
(Bit 6)
Bit 7 should be set to “1” to enable the CTCSS/DCS subaudio transmitter. The
subaudio Tx type will depend on the state of the SUBAUDIO TX MODE (Bit 1
SIGNALLING SET-UP Register $82).
Bit 6 should be set to “1” to enable the CTCSS/Selcall tone decoder or the DCS
decoder. Note: See also Bit 0 for DCS decoder operation.
Bits 7 and 6 should not both be set to “1” when Bit 0 is set to “1” because the
DCS function is half-duplex only.
CTCSS FAST
DETECT ENABLE
(Bit 5)
SELCALL TX
ENABLE
(Bit 2)
DCS RX ENABLE
(Bit 0)
When this bit is "1", the FAST CTCSS DETECT or FAST CTCSS PREDICTIVE
mode is enabled, depending upon the setting of FAST CTCSS MODE (Bit 3
SIGNALLING SET-UP Register, $82). When this bit is "0", both FAST CTCSS
DETECT and FAST CTCSS PREDICTIVE tone detectors are disabled.
When this bit is "1" the Selcall transmitter is enabled. When this bit is "0" the
Selcall transmitter is disabled and powersaved.
When this bit is "1" and Bit 6 is “1”, the DCS decoder is enabled. When this bit
is "0" the DCS decoder is disabled.
The DCS decoder and the subaudio (CTCSS or DCS) transmitter should not be
enabled at the same time.
(Bits 4, 3, and 1)
Reserved for future use. These bits should be set to "0".
©
2009 CML Microsystems Plc
10
D/828/4
CMLMICRO [ CML MICROCIRCUITS ]
