GMSK Modem Data Pump
Page 6 of 37
MX909A PRELIMINARY INFORMATION
4 General Description
This product has been designed to be compliant with the appropriate sections of the “Mobitex
Specification”.
TM
Interface
4.1
4.1.1
Description of Data Blocks
Data Bus Buffers
8 bi-directional, 3-state logic level buffers between the modem’s internal registers and the host
µ
C’s data bus
lines.
4.1.2
Address and R/W Decode
This block controls the transfer of data bytes between the
µ
C and the modem’s internal registers, according to
the state of the Write and Read Enable inputs (
WR
and
RD
), the Chip Select input
CS ), and the Register
Address inputs A0 and A1.
The Data Bus Buffers, Address, and R/W Decode blocks provide a byte-wide parallel
µ
C interface, which can
be memory mapped, as shown in Figure 3.
D0:7
A0:1
D0:7
A0:1
Data Bus
Address Bus
Address Decode
Circuit
A2:7
µC
IRQ
WR
RD
CS
V
DD
IRQ pull up
resistor
MODEM
IRQ
WR
RD
Figure 3: Typical Modem
µ
C Connections
4.1.3 Status and Data Quality Registers
8-bit registers which the µC can read to determine the status of the modem and the received data quality.
4.1.4 Command, Mode and Control Registers
The values written by the µC to these 8-bit registers control the operation of the modem.
4.1.5 Data Buffer
An 18-byte buffer used to hold receive or transmit data to or from the µC.
4.1.6 CRC Generator/Checker
A circuit which generates (in transmit mode) or checks (in receive mode) the Cyclic Redundancy Checksum
bits, which are included in transmitted Mobitex
¥
data blocks so the receive modem can detect transmission
errors.
4.1.7 FEC Generator/Checker
In transmit mode this circuit calculates and adds the Forward Error Correction (4 bits) to each byte presented
to it. In receive mode the FEC information is used to correct most transmission errors that have occurred in a
Mobitex
¥
Data Block or in the Frame Head control bytes.
4.1.8 Interleave / De-interleave Buffer
This circuit interleaves data bits within a data block before transmission and de-interleaves the received data
block so the FEC system is best able to handle short noise bursts or signal fades.
4.1.9 Frame Sync Detect
This circuit, (only active in receive mode), is used to look for the user specified 16-bit Frame Synchronization
pattern which is transmitted to mark the start of every frame.
¤
2001 MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480134.005
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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CMLMICRO [ CML MICROCIRCUITS ]
