1.0 Product Description
1.1 Pin Descriptions
CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
Table 1-2. Hardware Signal Definitions
(1 of 5)
Pin Label
ALE/PAREN
Signal Name
Address Latch
Enable/Parallel Input Enable
I/O
I
Definition
A dual-purpose active-high signal which, when
MON/MIC* is tied low, is microprocessor-generated
and causes the CN8330 to latch in the address on
the address-data bus. When MON/MIC* is tied high
(stand-alone mode), the parallel input for the PPDL
formatter is enabled. When this pin is tied low,
transmit data is sourced from the serial input
TDAT[6]/TXDAT.
(1)
A dual-purpose signal that enables read/write
functions when MON/MIC* is tied low, and controls
AIS transmission in stand-alone mode when
MON/MIC* is tied high. Both CS and ALM0 are
active high signals.
(1)
A dual-purpose signal that enables read data to be
passed to the address-data bus when MON/MIC* is
tied low, and controls idle code transmission in
stand-alone mode when MON/MIC* is tied high,
RD* is an active low signal and ALM1 is
active-high.
(1)
A dual-purpose signal that latches write data from
the address-data bus when MON/MIC* is tied low,
and controls the Cycle Redundancy Check (CRC)
when MON/MIC* is tied high. WR* is an active low
signal. In stand-alone mode, a high-speed 32-bit
CRC calculation is enabled if CRC32 is high; if low, a
16-bit calculation is performed.
(1)
Selects either microprocessor mode when tied low,
or stand-alone monitor mode when tied high. The
state of MON/MIC* determines which function the
dual-purpose pins (AD[7:0]) serve. The standalone
mode is valid only in DS3 mode.
(1)
Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating loss of signal.
(1)
Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating an out-of-frame state.
(1)
Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating alarm indication signal
detection.
(1)
Part of the bidirectional 8-bit multiplexed
address-data bus when MON/MIC* is tied low. When
in stand-alone mode, this pin is an active-high
monitor output indicating a yellow alarm.
(1)
CS/ALM0
Chip Select/Alarm 0
I
RD*/ALM1
Read/Alarm 1
I
WR*/CRC32
Microprocessor Interface
Write/Cycle Redundancy
Check 32
I
MON/MIC*
Monitor/Microprocessor
Mode Select
I
AD[0]/LOS
Address-Data 0/Loss of
Signal
B/O
AD[1]/OOF
Address-Data 1/Out of Frame
B/O
AD[2]/AIS
Address-Data 2/Alarm
Indication Signal
B/O
AD[3]/YEL
Address-Data 3/Yellow Alarm
Detection
B/O
1-8
Conexant
100441E
CONEXANT [ CONEXANT SYSTEMS, INC ]
