CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
The CN8330 is an integral DS3/E3 framer designed to support the transmission
formats defined by ANSI T1.107-1988, T1.107a-1989, T1.404, and ITU-T G.751
standards. All maintenance features required by Bellcore TR-TSY-000009 and AT&T
PUB 54014 are provided. In addition, the CN8330 can be optionally configured as a
High-Level Data Link Controller (HDLC) usable with or without DS3/E3 framing
overhead.
The CN8330 provides framing recovery for M13, C-bit parity, Syntran, and G.751
E3 formatted signals. A First In First Out (FIFO) buffer in the receive path can be
enabled to reduce jitter on the incoming data. Transmit and receive data is available to
the host in either serial or parallel byte and nibble formats. Access is provided to the
terminal data link and the Far End Alarm/Control (FEAC) channel, as specified in
T1.107a-1989. Counters are included for frame-bit errors, Line Code Violations
(LCVs), parity errors, and Far End Block Errors (FEBEs).
Two operational modes are available: microprocessor and stand-alone monitor
control modes. The microprocessor control mode monitors all status conditions and
provides configuration control. The stand-alone monitor mode allows the CN8330 to
operate as a monitor providing status and alarm information on external pins.
Distinguishing Features
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Supports DS3/E3 framing modes
Includes high-speed HDLC controller
(52 MHz)
Framing recovery for M13, C-bit
parity, Syntran, and G.751 E3 signals
Serial or parallel (octet or nibble)
interface modes
Average reframe time of less than
1 ms for DS3 and less than 250 µs
for E3
Supports the LAPD terminal data link
and FEAC channel as defined in
T1.107a-1989
68-pin PLCC or 80-pin MQFP
surface-mount package
Operates from a single +5 VDC ±5%
power supply
Low-power CMOS technology
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Functional Block Diagram
Applications
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Digital PCM switches
Digital Cross-Connect Systems
Channel Service Units (CSUs)
Channel extenders
ATM Switches/Concentrators
PBXs
Switched Multimegabit Digital
Service (SMDS) Equipment
Test equipment
Routers (including HSSI ports)
Bypass
RXPOS
RXNEG
DS3CKI
TXCKI
M
U
X
Unipolar
Conversion
FIFO
Framing
Recovery
RXMSY
CBITO
RXCCK
RXDAT
FIFO
Enable
Source
Loopback
Overhead/
Data Link
Processing
PPDL
Receiver
TXPOS
TXNEG
TCLKO
M
U
X
Bipolar
Encoder
RXCLK
Status
RDAT[7:0]
RXBCK
Status
Framing/
Overhead
Insertion
PPDL
Transmitter
Overhead/
Data Link
Processing
TXBCK
TDAT[7:0]
TXCCK
CBITI
TXCKI
Line
Loopback
AD[7:0]
Control
Microprocessor
Interface
To/From
All Blocks
TXDATI
TXSYI
Data Sheet
100441E
October 13, 1999
CONEXANT [ CONEXANT SYSTEMS, INC ]
