7.0 Electrical and Mechanical Specifications
CN8478/CN8474A/CN8472A/CN8471A
7.2 Timing and Switching Specifications
Multichannel Synchronous Communications Controller (MUSYCC™)
Table 7-7. PCI Reset Parameters
Symbol
Trst
Parameter
Reset Active Time after
Min
Max
Unit
1
—
ms
Power Stable
Trst_clk
Reset Active Time after
Clock Stable
100
—
µs
Nominal Voltage Level(1)
RST* Slew Rate(2)
Vnom
—
—
50
—
—
—
—
—
40
V
mV/ns
—
Power Failure Detect Time(3)
Reset Active to Float Delay
Tfail
Trst-off
ns
NOTE(S):
(1)
The nominal voltage level refers to a voltage test point in the power-up curve where the system can declare start of a “power
good” signal.
The minimum RST* slew rate applies only to the rising (deassertion) edge of the reset signal, and ensures that system noise
cannot render an otherwise monotonic signal to appear to bounce in the switching range.
The value of Tfail is the minimum of
(2)
(3)
a. 500 ns (max) from power rail going out of specification by exceeding specified tolerances by more than 500 mV.
b. 100 ns (max) from 5 V rail falling below 3.3 V rail by more than 300 mV.
Figure 7-2. PCI Reset Timing
Power
Power
Fail
V
nom
T
fail
PCLK
PWR_GOOD
PRST*
100 ms (typ)
T
rst
T
rst-clk
T
rst-off
Three-state
PCI
Signals
8478_025
7-6
Conexant
100660E
CONEXANT [ CONEXANT SYSTEMS, INC ]
