4.0 Serial Interface
CN8478/CN8474A/CN8472A/CN8471A
4.7 Tx and Rx FIFO Buffer Allocation and Management
Multichannel Synchronous Communications Controller
With no subchanneling, the Fixed Data Buffer area plus the Subchannel Map
area are available for Internal Data Buffer usage (total of 128 dwords). If the
buffer space is evenly divided across 32 channels, the BUFFLOC and BUFFLEN
specification is as listed in Table 4-4, for 32 channels without subchannel buffer
allocation.
Table 4-4. Example of 32-Channel without Subchanneling Buffer Allocation (Receive or Transmit)
Within Channel Descriptor
Channel
Number
BUFFLOC
(dword Offset from Start of
Fixed Data Buffer)
BUFFLEN(1)
0
1
0
2
1
1
2
4
1
...
31
...
62
...
1(2)
NOTE(S):
(1)
Assuming all channels within a group operate at the same bit rate, BUFFLEN = [(Total dwords ÷ Number of Channels) ÷ 2]–1.
BUFFLEN values larger than 1Fh do not increase the PCI burst length. BUFFLEN determines the number of dwords burst
during a PCI read/write operation to fill or flush the internal data buffer. For example, BUFFLEN = 1Fh specifies a burst length
of 32 dwords.
(2)
If the buffer space is evenly divided across 16 channels, the BUFFLOC and
BUFFLEN specification would be as listed in Table 4-5, for 16 channels with
subchannel buffer allocation.
Table 4-5. Example of 16-Channel without Subchanneling Buffer Allocation (Receive or Transmit)
Within Channel Descriptor
Channel
BUFFLOC
Number
(dword Offset from Start of
Fixed Data Buffer)
BUFFLEN(1)
0
1
0
4
3
3
2
8
3
...
15
...
60
...
3(2)
NOTE(S):
(1)
Assuming all channels within a group operate at the same bit rate, BUFFLEN = [(Total dwords ÷ Number of Channels) ÷ 2]–1.
BUFFLEN values larger than 1Fh do not increase the PCI burst length. BUFFLEN determines the number of dwords burst
during a PCI read/write operation to fill or flush the internal data buffer. For example, BUFFLEN = 1Fh specifies a burst length
of 32 dwords.
(2)
4-14
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