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interrupt request without masking out status bits to
determine the interrupt source.
Hardware Interface Signals
A functional interconnect diagram showing the typical
MDP connection in a system is illustrated in Figure 2. Any
point that is active low is represented by a small circle at
the signal point.
NRZI Encoding/Decoding
NRZI data encoding/decoding may be selected in
synchronous and HDLC modes instead of the default NRZ
(control bit NRZIEN). In NRZ encoding, a 1 is represented
by a high level and a 0 is represented by a low level. In
NRZI encoding, a 1 is represented by no change in level
and a 0 is represented by a change in level.
Edge triggered inputs are denoted by a small triangle
(e.g., TDCLK). An active low signal is indicated by a tilde
preceding the signal name (e.g., ~RESET).
A clock intended to activate logic on its rising edge (low-
to-high transition) is called active low (e.g., ~RDCLK),
while a clock intended to activate logic on its falling edge
(high-to-low transition) is called active high (e.g., TDCLK).
When a clock input is associated with a small circle, the
input activates on a falling edge. If no circle is shown, the
input activates on a rising edge.
ITU-T CRC-32 Support
ITU-T CRC-32 generation/checking may be selected
instead of the default ITU-T CRC-16 in HDLC mode using
DSP RAM access.
Caller ID Demodulation
Caller ID information can be demodulated in V.23 1200
receive configuration and presented to the host/DTE in
serial (RXD) and parallel (RBUFFER) form.
The 100-pin PQFP MDP hardware interface signals are
shown Figure 2.
The 100-pin PQFP MDP signal pin assignments are
shown Figure 3 and are listed in Table 4.
Telephone Line Interface
Line Transformer Interface. V.90/K56flex/V.34/V.32
bis/V.32 places high requirements upon the Data Access
Arrangement (DAA) to the telephone line. Any non-linear
distortion generated by the DAA in the transmit direction
cannot be canceled by the MDP's echo canceller and
interferes with data reception. The designer must,
therefore, ensure that the total harmonic distortion seen at
the RXA input to the MDP be at least 65 dB below the
minimum level of received signal. Due to the wider
bandwidth requirements in V.90, K56flex, and V.34, the
DAA must maintain linearity from 10 Hz to 4000 Hz.
The MDP hardware interface signals are described in
Table 5.
The digital interface characteristics are defined in Table 6.
The analog interface characteristics are defined Table 7.
The power requirements are defined in Table 8.
The absolute maximum ratings are defined in Table 9.
Relay Control. Direct control of the off-hook and talk/data
relays is provided. Internal relay drivers allow direct
connection to the off-hook (RLYA) and talk/data (RLYB)
relays. The talk/data relay output can optionally be used
for pulse dial.
Speaker Interface
An analog speaker output (SPK) is provided with on/off
and volume control logic incorporated in the MDP. An
external amplifier is recommended if driving non-amplified
speakers.
A digital speaker output (SPKMD) is provided which
reflects the received analog input signal digitized to TTL
high or low level by an internal comparator to create a PC
Card (PCMCIA)-compatible signal.
Additional Information
Additional information is provided in the RP56D, RP336D,
and RP144D Modem Designer's Guide (Order No. 1155).
CONEXANT [ CONEXANT SYSTEMS, INC ]
