RS8953B/8953SPB
HDSL Channel Unit
The RS8953B is a High-Bit-Rate Digital Subscriber Line (HDSL) channel unit designed
to perform data, clock, and format conversions necessary to construct a Pulse Code
Multiplexed (PCM) channel from one, two, or three HDSL channels. The PCM channel
consists of transmit and receive data, clock and frame sync signals configured for
standard T1 (1544 kbps), standard E1 (2048 kbps), or custom (Nx64 kbps) formats.
The PCM channel connects directly to a Bt8370 T1/E1 Controller or similar T1/E1 device.
Connection to other network/subscriber physical layer devices is supported by the
custom PCM frame format. Three identical HDSL channel interfaces consist of serial
data and clock connected to a Bt8970 HDSL Transceiver or similar 2B1Q bit pump
device. The RS8953SPB contains one HDSL channel interface.
Control and status registers are accessed via the Microprocessor Unit (MPU)
interface. One common register group configures the PCM interface formatter,
Pseudo-Random Bit Sequence (PRBS) generator, Bit Error Rate (BER) meter, timeslot
router, Digital Phase Lock Loop (DPLL) clock recovery, and PCM Loopbacks (LB). Three
groups of HDSL channel registers configure the elastic store FIFOs, overhead MUXes,
receive framers, payload mappers, and HDSL loopbacks. Status registers monitor
received overhead, DPLL, FIFO, and framer operations, including CRC and FEBE error
counts.
The RS8953B adheres to Bellcore TA-NWT-001210 and FA-NWT-001211 and the
latest ETSI RTR/TM-03036 standards. C-language software for all standard T1/E1
configuration and startup procedures is implemented on Conexant's HDSL Evaluation
Module (Bt8973EVM) and is available under a no-fee license agreement. RS8953B
software can also be developed for non-standard HDSL applications or to interoperate
with existing HDSL equipment.
Distinguishing Features
Supports All HDSL Bit Rates
– 2 pair T1 standard (784 kbps)
– 2 pair E1 standard (1168 kbps)
– 3 pair E1 standard (784 kbps)
– 1/2/3 pair custom (Nx64 kbps,
N=2-36)
• T1/E1 Primary Rate (PCM) Channel
– Connects to Conexant E1/T1
Framers
– Framed or unframed mode
– Sync/Async payload mapping
– Clock recovery/jitter attenuation
– PRBS/fixed test patterns
– BER measurement
• HDSL Channels
– Connects to Conexant ZipWire
Transceivers
– Three independent serial channels
– Central, remote, or repeater
– Overhead (HOH) management
– Programmable path delays
– Error performance monitoring
– Software controlled EOC and IND
– Auxiliary payload/Z-bit data link
– Master loop ID and interchange
– Auto tip/ring reversal
• Programmable Data Routing
– PCM timeslots – HDSL payload
– Drop/Insert – HDSL payload
– Auxiliary – HDSL payload
– PRBS/Fixed – PCM or HDSL
– PCM and HDSL loopbacks
• Intel
®
or Motorola
®
MPU interface
• CMOS technology, 3.3 V operation
• 68-pin PLCC or 80-pin PQFP
•
Functional Block Diagram
Timeslot Router
PCM Formatter
Drop
Insert
Elastic
Store
Mapper
HOH Mux
2B1Q
Encoder
HDSL
Channels
1, 2, 3
PRBS
LB
BER
Stuff
LB
PCM
Channel
Elastic
Store
Payload
Mapper
2B1Q
Decoder
Applications
•
•
•
•
•
•
•
•
Full, Fractional or Multipoint T1/E1
Single and Multichannel Repeaters
Voice Pair Gain Systems
Wireless LAN/PBX
PCS, Cellular Base Station
Fiber Access/Distribution
Loop Carrier, Remote Switches
Subscriber Line Modem
MPU
Registers
DPLL
Receive
Framer
Microprocessor
PLL Filter
Data Sheet
D8953BDSB
March 30, 1999
CONEXANT [ CONEXANT SYSTEMS, INC ]
