2.0 Pin Descriptions
RS8953B/8953SPB
2.2 Signal Definitions
HDSL Channel Unit
Table 2-2. Signal Definitions (4 of 4)
Signal
Name
I/O
Description
Drop/Insert
DROP
Drop Indicator
O
Active-high output indicates when specific PCM timeslots are present on RSER.
DROP is high for 8 bits coincident with each marked timeslot, or 1 bit when
marking F-bits. Any combination of timeslots and F-bits within the PCM frame
can be marked.
I(1)
INSDAT
INSERT
Insert Data
Alternate source of PCM transmit serial data. INSDAT is sampled by TCLK and
replaces TSER when INSERT is active. INSDAT and TSER use the same frame
format. INSDAT can be programmed to replace TSER data on a
per-timeslot-basis.
Insert Indicator
O
Active-high output indicates when specific INSDAT timeslots are sampled.
INSERT is high for 8 bits coincident with each marked timeslot or for 1 bit when
marking F-bits. Any combination of timeslots and F-bits within the PCM frame
can be marked.
DPLL and Power
MCLK
Master Clock
I
Runs through a multiplier PLL to create an internal 60–80 MHz reference clock
for the DPLL. The 16 times symbol rate clock from a Conexant HDSL transceiver
typically connects to MCLK. However, MCLK is not required to be synchronized
to any HDSL or PCM channel. The DPLL reference clock is used to synthesize
the PCM Recovered Clock (RCLK) based on DPLL programmed values.
Optionally, a 60–80 MHz clock can be input directly on MCLK.
SCLK
VEXT
System Clock
O
I
The internal 60–80 MHz DPLL reference clock is divided by 4 to create a
15–20 MHz system clock output on SCLK. SCLK can be applied to other devices
requiring a system clock (i.e., Bt8360 or Bt8510).
External Voltage
Used to bias input protection diodes. If interfacing to 5 V powered devices,
connect this pin to 5 V. Otherwise, connect 3.3 V to this pin.
PLLVCC
PLL Power
I
I
I
3.3 Vdc +/– 0.3 V power input for the PLL.
0 Vdc ground reference for the PLL.
PLLDGND
PLLAGND
PLL Ground
PLL Analog
Ground
0 Vdc analog ground reference for the PLL. Tied to GND unless PLL operation is
desired above 80 MHz.
VCC
GND
TCK
TMS
Power
I
I
I
3.3 Vdc +/– 0.3 V power input.
Ground
0 Vdc ground reference.
Test Clock
Test Mode Select
Boundary scan clock samples and outputs test access signals.
Active-high enables test access port. Sampled by TCK rising edge.
I(1)
I(1)
O
TDI
Test Data Input
Serial data for boundary scan chain. Sampled by TCK rising edge.
Outputs serial data from boundary scan chain on TCK falling edge.
TDO
Test Data Output
NOTE(S):
(1)
Internal pull-ups (80-100 kW) are present on inputs to allow unused inputs to remain disconnected.
Internal pull-downs (80-100 kW) are present on inputs to allow unused inputs to remain disconnected.
The pins do not perform these functions in RS8953SPBEPF and RS8953SPBEPJ.
(2)
(3)
2-10
Conexant
N8953BDSB
CONEXANT [ CONEXANT SYSTEMS, INC ]
