RS8953B/8953SPB
4.0 Registers
HDSL Channel Unit
4.6 PCM Formatter
4.6 PCM Formatter
Table 4-4. PCM Formatter Write Registers
Address
Register Label
TFRAME_LOC_LO
Bits
Name/Description
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
8
1
6
8
1
6
6
6
8
1
TSER Frame Bit Location
TSER Frame Bit Location
TFRAME_LOC_HI
TMF_LOC
TSER Multiframe Location
RSER Frame Bit Location
RSER Frame Bit Location
RSER Multiframe Location
PCM Multiframe Length
PCM Multiframes per HDSL Frame
PCM Frame Length
RFRAME_LOC_LO
RFRAME_LOC_LO
RMF_LOC
MF_LEN
MF_CNT
FRAME_LEN_LO
FRAME_LEN_LO
PCM Frame Length
The PCM formatter supports connections to many types of PCM channels by allowing the system to define the
PCM bus format and sync timing characteristics. PCM frame length, multiframe length, and PCM multiframes
per HDSL frame are programmed in the PCM formatter registers to define receive and transmit timebases.
Programmed frame and multiframe lengths for both timebases allows the RS8953B to continue operating at
appropriate intervals when PCM transmit sync or HDSL receive sync references are lost, and when RS8953B
acts as the PCM bus master. The transmit timebase controls the routing of PCM timeslots into the transmit
FIFOs, while the receive timebase controls the extraction of PCM timeslots out of the receive FIFOs. The
number of multiframes per HDSL frame is needed to generate PCM 6 ms timebases used for transmit bit
stuffing and Digital Phase Lock Loop (DPLL) receive clock recovery.
PCM formatter configuration registers also define the PCM timing relationships between transmit data
(TSER, INSDAT) and sync (TMSYNC, MSYNC), and receive data (RSER) and sync (RMSYNC). TMSYNC is
delayed by a programmed number of bits and frames to create the MSYNC output signal. MSYNC is then used
to locate the first bit (bit 0) of a frame, and the first frame (frame0) of a multiframe at the TSER input. MSYNC
is always used to align both PCM and HDSL transmit timebases, regardless of whether TMSYNC is applied.
RMSYNC is output from the receive PCM timebase after it is delayed by a programmed number of bits and
frames.
NOTE:
The internal PCM receive timebase is frame and multiframe aligned with respect to
the master HDSL channel’s receive 6 ms frames [refer to RFIFO_WL; addr 0xCD].
The internal PCM receive timebase is not affected by programmed bit and frame
delays for RMSYNC.
N8953BDSB
Conexant
4-25
CONEXANT [ CONEXANT SYSTEMS, INC ]
