Register Descriptions and Operation
Chip_ID_low, 0x00 (R)
Bit 7 ~ Bit 0
Low byte of chip ID: 0x12
Chip_ID_High, 0x01 (R)
Bit 7 ~ Bit 0
High byte of chip ID: 0x30
Chip_Revision, 0x02 (R)
Bit 7 ~ Bit 0
Chip revision number: Chip revision number is subject to change.
Bandwidth, 0x03 (R/W)
Bit 7 ~ Bit 5
Reserved
Bit 4
Reserved
0:Default
Bit 3 ~ Bit 0
Bandwidth Selection in Hz:
0000: 0.025
0001: 0.025
0010: 0.025
0011: 0.025
0100: 0.025
0101: 0.025
0110: 0.049
0111: 0.098(Reset Default)
1000: 0.20
1001: 0.39
1010: 0.78
1011 - 1111: 1.6
BITS 3 - 0 select the phase lock loop bandwidth in Hertz. The reset default is 0.098 Hz.
Ctl_Mode, 0x04 (R/W)
Bit 7 ~ Bit 6
Reserved
Bit 5
Default: 0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
M/S Output
BITS Clock
HM Ref:
Active
Reserved
Pulse width
Output
0: Register control
Reference
control:
Frequency:
of op mode/ref
Selection:
0: 50%
1: 1.544 MHz
(Will always
1: Manual
1: Controlled by
0: 2.048 MHz
be 0)
0: Automatic
FR_Pulse_Width (read only)
Default: 1
register
Default: 0
When bit 1 is reset (automatic reference and mode selection), Bits 3 - 0 of the
Op_Mode
register become read-only.
The power-up default for Bit 1 = 1 for manual reference selection and default for Bit 4 = 0 for 50% duty cycle on
M/S Output.
Data Sheet #:
TM052
Page 12
of
36
Rev:
03
Date:
11/07/08
© Copyright 2008 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
CONNOR-WINFIELD [ CONNOR-WINFIELD CORPORATION ]
