Synchronous Clock for SETS
Data Sheet
Description
The STC4130 is a ROHS compatible, integrated,
single chip solution for the synchronous clock in SDH
and SONET network elements. The device is fully
compliant with ITU-T G.812 Type III, G.813, and
Telcordia GR1244, and GR253.
The STC4130 accepts 12 reference inputs and gen-
erates 8 independent synchronized output clocks.
Reference input frequencies are automatically
detected, and inputs are individually monitored for
quality. Active reference selection may be manual or
automatic. All reference switches are hitless. Syn-
chronized outputs may be programmed for a wide
variety of SONET and SDH frequencies.
Two independent clock generators provide the stan-
dardized T0 and T4 functions. Each clock generator
includes a DPLL (Digital Phase-Locked Loop), which
may operate in the Freerun, Synchronized, and Hold-
over modes. Both clock generators support master/
slave operation for redundant applications. Connor-
Winfield’s proprietary
SyncLink
TM
Cross-couple data
link provides master/slave phase information and
state data to ensure seamless side switches.
A standard SPI serial bus interface or parallel bus
provide access to the STC4130’s comprehensive, yet
simple to use internal control and status registers.
The device operates with an external OCXO or TCXO
as its MCLK at either 10 or 20 MHz.
STC4130
Features
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Functional Specification
For SDH SETS and SSU
For SONET Stratum 3E, 3, 4E, 4 and SMC
Complies with ITU-T G.812 Type III , G.813, Tel-
cordia GR1244, and GR253
Supports Master/Slave operation with the
SyncLink
TM
cross-couple data link for master/
slave redundant applications
Accepts 12 individual clock reference inputs
Reference clock inputs are automatically fre-
quency detected
Supports manual or automatic reference selec-
tion
T0 and T4 have independent reference lists and
priority tables for automatic reference selection
8 synchronized output clocks
Output/input phase skew is adjustable in slave
mode, in 0.1nS steps up to 200nS
Hit-less reference and master/slave switching
Phase rebuild on re-lock and reference switches
Better than 0.1 ppb holdover accuracy
Programmable bandwidth, from 90mHz to 107Hz,
for both T0 and T4 DPLL
Supports SPI or parallel bus interface
IEEE 1149.1 JTAG boundary scan
Available in TQ100 ROHS package
T0_Master_Slave
T0_Xsync_In
Phase
Detector
Digital
Filter
LVDS 155.52 MHz
19.44/38.88/77.76 MHz
19.44/38.88/77.76 MHz
T0 Active
Ref Selector
Reference Clk
8 KHz
64 KHz
1.544 MHz
2.048 MHz
19.44 MHz
38.88 MHz
77.76 MHz
12
Activity &
Frequency
Offset Monitor
T4 Active
Ref Selector
To
Clock
Generator
8 KHz
2 KHz
1.544/3.088/6.176/12.352/24.704 MHz
2.048/4.096/8.192/16.384/32.768 MHZ
44.736 MHz/34.368 MHz
T0_Xsync_Out
STC4130
T4_Xsync_In
T4_Master_Slave
OCXO
TCXO
10MHz/
20MHz
Phase
Detector
Digital
Filter
T4
Clock
Generator
1.544 MHz/2.048 MHz
T4_Xsync_Out
Serial/Parallel Bus
Interface
Control & Status
Registers
IEE 1194.1
JTAG
Figure 1: Functional Block Diagram
Data Sheet #:
TM084
© Copyright 2006 The Connor-Winfield Corp.
Page 1 of 44
Rev: P02
Date: 12/5/06
All Rights Reserved
Specifications subject to change without notice
CONNOR-WINFIELD [ CONNOR-WINFIELD CORPORATION ]
