Synchronous Clock for SETS
Data Sheet
Description
The STC5230 is a single chip solution of timing source
in SDH, SONET, and Synchronous Ethernet network
elements. The device is fully compliant with ITU-T
G.813, and Telcordia GR1244, and GR253.
The STC5230 accepts 12 reference inputs and gener-
ates 9 independent synchronized output clocks. Refer-
ence input frequencies are automatically detected, and
inputs are individually monitored for quality. Active refer-
ence selection may be manual or automatic. All refer-
ence switches are hitless. Synchronized outputs may be
programmed for a wide variety of SONET and SDH as
well as Synchronous Ethernet frequencies.
Two independent timing generators, T0 and T4, provide
the essential functions for Synchronous Equipment Tim-
ing Source (SETS). Each timing generator includes a
DPLL (Digital Phase-Locked Loop), which may operate
in the Freerun, Synchronized, and Holdover modes.
Both timing generators support master/slave operation
for redundant applications. The proprietary
SyncLink
TM
cross-couple data link provides master/slave phase
information and state data to ensure seamless side
switches.
A standard SPI serial bus interface provide access to the
STC5230’s comprehensive, yet simple to use internal
control and status registers. The device operates with an
external OCXO or TCXO as its MCLK at 20 MHz.
The STC5230 is capable of field upgrade with optional
external EEPROM or via the bus interface.
STC5230
Features
Functional Specification
- For SDH SETS, SONET Stratum 3, 4E, 4 and
SMC, and
Synchronous Ethernet
- Two timing generators, T0 and T4, for SETS
- Complies with ITU-T G.813, Telcordia GR1244 and
GR253
- Supports Master/Slave redundant application with
the
SyncLink
TM
cross-couple data links
- Accepts 12 individual clock reference inputs
- Reference clock inputs are automatically frequency
detected; each is monitored for quality
- Support manual and automatic reference selection
- T0 and T4 have independent reference lists and
priority tables for automatic reference selection
- Output 9 synchronized clocks
- Could compensate the phase delay of the cross-
couple links, in 0.1ns steps up to 409.5ns
- Capable to trace the round-trip phase delay of the
master/slave cross-couple links.
- Hit-less reference and master/slave switching
- Phase rebuild on re-lock and reference switches
- Programmable loop bandwidth of each DPLL of the
T0 and T4 timing generator, from 90mHz to 107Hz
- Supports SPI bus interface
- Field upgrade capability
- IEEE 1149.1 JTAG boundary scan
- Available in TQFP100 package
T0_MASTER_SLAVE
T0_XSYNC_IN
Phase
Detector
Digital
Filter
LVPECL 155.52/125 MHz
19.44/38.88/51.84/77.76/25/50/125 MHz
19.44/38.88/51.84/77.76/25/50/125 MHz
T0 Active
Ref Selector
12
Reference Clk
8 kHz
64 kHz
1.544 MHz
2.048 MHz
19.44 MHz
38.88 MHz
77.76 MHz
6.48 MHz
8.192 MHz
16.384 MHz
25 MHz
50 MHz
125 MHz
T0
Clock
Synthesizer
8 kHz
2 kHz
1.544/3.088/6.176/12.352/24.704 MHz
2.048/4.096/8.192/16.384/32.768 MHz
44.736 MHz/34.368 MHz
LVPECL 155.52/125 MHz (2
nd
)
Activity &
Frequency
Offset Monitor
T4 Active
Ref Selector
STC5230
T0_XSYNC_OUT
Phase
Detector
Digital
Filter
T4
Clock
Synthesizer
1.544 MHz/2.048 MHz
T4_Xsync_Out
T4_XSYNC_In
T4_Master_Slave
OCXO
TCXO
20MHz
Serial Bus
Interface
Control & Status
Registers
IEEE 1194.1
JTAG
Figure 1: Functional Block Diagram
Preliminary
Data Sheet #:
TM102
Page 1 of 48
Rev: P01
Date: August 22, 2007
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
CONNOR-WINFIELD [ CONNOR-WINFIELD CORPORATION ]
