Model 114
Dual-In-Line Stratum 3 OCXO
♦
Frequency Stability to Stratum 3 of GR-1244
♦
Low Cost ASIC Based Design
♦
Very Low Phase Jitter: < 1 pSec
♦
+3.3Vdc or +5.0Vdc Operation
♦
Precision Low Aging “AT” Cut Crystal
♦
Through-Hole or Surface Mount Configuration
♦
6/6 RoHS Compliant
Electrical Characteristics
Parameter
Power Requirements
Power Supply
Turn-On Power
Steady State Power
V
cc
P
max
P
ss
Sym
Conditions
±
5%
114L
±
5%
114S
Vcc=Max.
Std. Load
Vcc=Max.
Std. Load
@ +25°C
To within
±
0.3ppm
@ +25°C
Min
3.135
4.75
Typical
3.30
5.0
3.5
1.5
Max
3.465
5.25
4.0
Unit
Vdc
Vdc
W
W
Warm-Up Time
Frequency Stabilities
Center Frequency
Twu
5
minutes
f
nom
8
Initial Tolerance
Freq. vs. Temp.
Freq. vs. Voltage
Freq. vs Time (Aging)
24 Hour Holdover
Stability
Total Free-Running
Accuracy
Electronic Frequency
Adjust (Optional)
Waveform: CMOS
Output
Symmetry
Amplitude
Rise/Fall Times
Load
Phase Noise
@ f
o
=20MHz
f
cal
∆f/∆Temp
∆f/∆Vcc
∆f/∆Time
∆f/24Hr
∆f/Life
∆f/Vc
Ta=+25°C
(At time of Shipment)
0° to +70°C
-40° to +85°C
Vcc
±5%
Per day
20 years
Inclusive of Temp.,
Supply Variation and
24Hrs. Aging
All Cond. for 20 Yrs.
(Ref. to f
nom
)
f
min
@ Vc=0V
f
max
@ Vc=Vcc
f
nom
@Vc=0.5Vcc
10
12.8
16.384
19.44
20
±0.1
±0.075
±0.150
±
0.05
±0.005
±2.5
±0.20
38.88
MHz
ppm
±0.125
±0.250
ppm
ppm
ppm
±0.37
±4.6
ppm
ppm
ppm
±9.2
Sym
Vo
tr, tf
RL
Pn
@ 50% Level
Logic “1”
Logic “0”
20% to 80%
Output to Ground
Offset = 10Hz
100Hz
1kHz
10kHz
100kHz
12kHz to 20MHz
Bandwidth
40
0.9Vcc
50
60
0.1Vcc
10
6
10kΩ // 15pF
-80
-115
-135
-140
-143
%
V
V
ns
Phase Jitter
1.0
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps RMS
♦♦♦
CTS
♦
171 Covington Dr.
♦
Bloomingdale, IL 60108
♦
800-757-6686
♦
www.ctscorp.com
♦♦♦
Document No. 114 Data Sheet
Page 1 of 2
Rev X8
CTS [ CTS CORPORATION ]
