CY23S09
CY23S05
Select Input Decoding for CY23S09
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Three-state
Driven
Driven
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
Driven
CLKOUT
[1]
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shut-down
N
N
Y
N
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs,
including CLKOUT, must be equally loaded. Even if CLKOUT
is not used, it must have a capacitive load equal to that on
other outputs, for obtaining zero input-output delay. If input to
output delay adjustments are required, use the above graph to
calculate loading differences between the CLKOUT pin and
other outputs.
For zero output-output skew, be sure to load all outputs
equally. For further information, refer to the application note
“CY23S05 and CY23S09 as PCI and SDRAM Buffers.”
Spread Aware
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we
designed this product so as not to filter off the Spread
Spectrum feature of the Reference input, assuming it exists.
When a zero delay buffer is not designed to pass the SS
feature through, the result is a significant amount of tracking
skew which may cause problems in systems requiring
synchronization.
For more details on Spread Spectrum timing technology,
please see the Cypress application note entitled, “EMI
Suppression Techniques with Spread Spectrum Frequency
Timing Generator (SSFTG) ICs.”
Pin Description for CY23S09
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
[2]
CLKA1
[3]
CLKA2
[3]
V
DD
GND
CLKB1
[3]
CLKB2
[3]
S2
[4]
S1
[4]
CLKB3
[3]
CLKB4
[3]
GND
V
DD
CLKA3
[3]
CLKA4
[3]
CLKOUT
[3]
Signal
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
Ground
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, bank B
Buffered clock output, bank B
Ground
3.3V supply
Buffered clock output, bank A
Buffered clock output, bank A
Buffered output, internal feedback on this pin
Description
Input reference frequency, 5V-tolerant input
Notes:
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
2. Weak pull-down.
3. Weak pull-down on all outputs.
4. Weak pull-up on these inputs.
Document #: 38-07296 Rev. *C
Page 2 of 9
CYPRESS [ CYPRESS SEMICONDUCTOR ]
