MoBL
®
CY62128E
1-Mbit (128K x 8) Static RAM
Features
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Functional Description
The CY62128E
is a high performance CMOS static RAM
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99 percent when deselected (CE
1
HIGH or CE
2
LOW). The
eight input and output pins (IO
0
through IO
7
) are placed in a high
impedance state when the device is deselected (CE
1
HIGH or
CE
2
LOW), the outputs are disabled (OE HIGH), or a write
operation is in progress (CE
1
LOW and CE
2
HIGH and WE LOW)
To write to the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. Data on the eight IO
pins (IO
0
through IO
7
) is then written into the location specified
on the address pins (A
0
through A
16
).
To read from the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the IO pins.
Very high speed: 45 ns
Temperature ranges
❐
Industrial: –40°C to +85°C
❐
Automotive-A: –40°C to +85°C
❐
Automotive-E: –40°C to +125°C
Voltage range: 4.5V to 5.5V
Pin compatible with CY62128B
Ultra low standby power
❐
Typical standby current: 1
μA
❐
Maximum standby current: 4
μA
(Industrial)
Ultra low active power
❐
Typical active current: 1.3 mA at f = 1 MHz
Easy memory expansion with CE
1
, CE
2,
and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Offered in standard Pb-free 32-pin STSOP, 32-pin SOIC, and
32-pin TSOP I packages
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Logic Block Diagram
CE1
CE2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
WE
OE
INPUT BUFFER
IO0
IO1
SENSE AMPS
IO2
IO3
IO4
IO5
IO6
ROW DECODER
128K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
IO7
A12
A13
A14
A15
Note
1. For best practice recommendations, refer to the Cypress application note
“System Design Guidelines”
at
A16
Cypress Semiconductor Corporation
Document #: 38-05485 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 4, 2008
CYPRESS [ CYPRESS SEMICONDUCTOR ]
