PRELIMINARY
Switching Waveforms
Read Cycle No.1
[8, 9]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
CY6264
CY6264-5
Read Cycle No. 2
[10, 11]
CE
1
t
RC
CE
2
OE
OE
t
ACE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
ICC
50%
ISB
CY6264-6
HIGH
IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)
[9, 11]
t
WC
ADDRESS
t
SCE1
CE
1
CE
2
t
SCE2
OE
t
AW
WE
t
SA
t
PWE
t
HA
t
SD
DATA IN
DATA
IN
VALID
t
HZWE
DATA I/O
DATA UNDEFINED
t
HD
t
LZWE
HIGH IMPEDANCE
CY6264-7
Notes:
8. Device is continuously selected. OE, CE = V
IL
. CE
2
= V
IH.
9. Address valid prior to or coincident with CE transition LOW.
10. WE is HIGH for read cycle.
11. Data I/O is High Z if OE = V
IH
, CE
1
= V
IH
, or WE = V
IL
.
4
CYPRESS [ CYPRESS SEMICONDUCTOR ]
