CY7B923
CY7B933
Pin Descriptions
CY7B923 HOTLink Transmitter
Name
D
0−7
(D
b
−
h
)
SC/D (D
a
)
I/O
TTL In
Description
Parallel Data Input.
Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW (or
on the next rising CKW with ENN LOW). If ENA and ENN are HIGH, a Null character (K28.5) is sent.
When MODE is HIGH, D
0, 1, ...7
become D
b, c,...h
, respectively.
Special Character/Data Select.
A HIGH on SC/D when CKW rises causes the transmitter to encode
the pattern on D
0−7
as a control code (Special Character), while a LOW causes the data to be coded
using the 8B/10B data alphabet. When MODE is HIGH, SC/D (D
a
) acts as D
a
input. SC/D has the
same timing as D
0−7
.
Send Violation Symbol.
If SVS is HIGH when CKW rises, a Violation symbol is encoded and sent
while the data on the parallel inputs is ignored. If SVS is LOW, the state of D
0−7
and SC/D determines
the code sent. In normal or test mode, this pin overrides the BIST generator and forces the transmission
of a Violation code. When MODE is HIGH (placing the transmitter in unencoded mode), SVS (D
j
) acts
as the D
j
input. SVS has the same timing as D
0−7
.
Enable Parallel Data.
If ENA is LOW on the rising edge of CKW, the data is loaded, encoded, and
sent. If ENA and ENN are HIGH, the data inputs are ignored and the Transmitter will insert a Null
character (K28.5) to fill the space between user data. ENA may be held HIGH/LOW continuously or it
may be pulsed with each data byte to be sent. If ENA is being used for data control, ENN will normally
be strapped HIGH, but can be used for BIST function control.
Enable Next Parallel Data.
If ENN is LOW, the data appearing on D
0−7
at the next rising edge of CKW
is loaded, encoded, and sent. If ENA and ENN are HIGH, the data appearing on D
0−7
at the next rising
edge of CKW will be ignored and the Transmitter will insert a Null character to fill the space between
user data. ENN may be held HIGH/LOW continuously or it may be pulsed with each data byte sent. If
ENN is being used for data control, ENA will normally be strapped HIGH, but can be used for BIST
function control.
Clock Write.
CKW is both the clock frequency reference for the multiplying PLL that generates the
high-speed transmit clock, and the byte rate write signal that synchronizes the parallel data input. CKW
must be connected to a crystal controlled time base that runs within the specified frequency range of
the Transmitter and Receiver.
Fiber Optic Transmitter Off.
FOTO determines the function of two of the three PECL transmitter
output pairs. If FOTO is LOW, the data encoded by the Transmitter will appear at the outputs contin-
uously. If FOTO is HIGH, OUTA± and OUTB± are forced to their “logic zero” state (OUT+ = LOW and
OUT− = HIGH), causing a fiber-optic transmit module to extinguish its light output. OUTC is unaffected
by the level on FOTO, and can be used as a loop-back signal source for board-level diagnostic testing.
TTL In
SVS
(D
j
)
TTL In
ENA
TTL In
ENN
TTL In
CKW
TTL In
FOTO
TTL In
OUTA±
OUTB±
OUTC±
PECL Out
Differential Serial Data Outputs.
These PECL 100K outputs (+5V referenced) are capable of driving
terminated transmission lines or commercial fiber optic transmitter modules. Unused pairs of outputs
can be left open, or wired to V
CC
to reduce power, if the output is not required. OUTA± and OUTB±
are controlled by the level on FOTO, and will remain at their “logical zero” states when FOTO is
asserted. OUTC± is unaffected by the level on FOTO. (OUTA+ and OUTB+ are used as a differential
test clock input while in Test mode, i.e., MODE = UNCONNECTED or forced to V
CC/2
.)
Three-
Level In
Encoder Mode Select.
The level on MODE determines the encoding method to be used. When wired
to GND, MODE selects 8B/10B encoding. When wired to V
CC
, data inputs bypass the encoder and
the bit pattern on D
a–j
goes directly to the shifter. When left floating (internal resistors hold the input at
V
CC
/2) the internal bit-clock generator is disabled and OUTA+/OUTB+ become the differential bit clock
to be used for factory test. In typical applications MODE is wired to V
CC
or GND.
BIST Enable.
When BISTEN is LOW and ENA and ENN are HIGH, the transmitter sends an alternating
1–0 pattern (D10.2 or D21.5). When either ENA or ENN is set LOW and BISTEN is LOW, the transmitter
begins a repeating test sequence that allows the Transmitter and Receiver to work together to test the
function of the entire link. In normal use this input is held HIGH or wired to V
CC
. The BIST generator
is a free-running pattern generator that need not be initialized, but if required, the BIST sequence can
be initialized by momentarily asserting SVS while BISTEN is LOW. BISTEN has the same timing as
D
0-7
.
Read Pulse.
RP is a 60% LOW duty-cycle byte-rate pulse train suitable for the read pulse in CY7C42X
FIFOs. The frequency on RP is the same as CKW when enabled by ENA, and duty cycle is independent
of the CKW duty cycle. Pulse widths are set by logic internal to the transmitter. In BIST mode, RP will
remain HIGH for all but the last byte of a test loop. RP will pulse LOW one byte time per BIST loop.
MODE
BISTEN
TTL In
RP
TTL Out
Document #: 38-02017 Rev. *E
Page 3 of 33
CYPRESS [ CYPRESS SEMICONDUCTOR ]
